NEW
Font size
WorksheetsIHDL_SEMFQUIZ
Total questions: 20
Worksheet time: 15mins
What is the main purpose of a Verilog testbench?
To synthesize hardware
To simulate and verify the design
To generate RTL code
To program an FPGA
A testbench is NOT allowed to contain which of the following?
initial blocks
Delay statements (#10)
$display statements
Input/output ports
In a testbench, signals connected to the DUT inputs must be declared as:
wire
reg/logic
integer
parameter
What does the $monitor system task do?
Ends the simulation
Prints signal changes whenever they occur
Dumps waveform values
Generates random test vectors
Which Verilog construct groups multiple signals?
begin
assign
{A, B}
@(*)
A Verilog module used inside a testbench is called a:
Prototype
Function
Instance
Class
In behavioral modeling, which block describes combinational logic?
always @(*)
always @(posedge clk)
initial
assign
Which of the following is TRUE about behavioral modeling?
Uses logic gates only
Describes how the circuit behaves
Cannot model combinational logic
Requires FPGA hardware
Which statement is used for decision-making in behavioral Verilog?
loop
assign
if-else
@()
A testbench starts execution automatically because it uses:
always blocks
Modules
initial blocks
function blocks
Which statement ends a simulation?
$display
$finish
$stop
endmodule
In behavioral modeling, which type of assignment is typically used for combinational logic?
Non-blocking (<=)
Blocking (=)
Both A and B
Only assign
What is the sensitivity list for combinational logic?
@(posedge clk)
@(negedge clk)
@(*)
@(A or B)
A minimal testbench must include:
A clock
Looping logic
DUT instantiation
Random vectors
What does {A, B, C} = 3'b101; do?
Assigns A=0, B=0, C=0
Assigns A=1, B=0, C=1
Assigns A=1, B=1, C=0
Causes an error
Which keyword is required for behavioral conditional logic?
defparam
fork
if / else
always_ff
Which type of Verilog description is best for large digital systems?
Gate-level modeling
Behavioral modeling
Switch-level modeling
Transistor-level modeling
What is a characteristic of combinational logic?
Depends only on current inputs
Requires a clock
Stores data
Always sequential
Which of the following is NOT a valid data type in Verilog?
wire
integer
reg
float
What does the 'posedge' keyword signify in Verilog?
Falling edge of a clock signal
High logic level
Rising edge of a clock signal
Low logic level
