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WorksheetsDCDV_AAT_QUIZ
Total questions: 10
Worksheet time: 10mins
How is a Verilog module delimited in source code?
Begins with module, ends with endmodule
Begins with begin, ends with end
Begins with module;, ends with ;endmodule;
Begins with module, ends with end
What is true about Verilog keywords with respect to case?
All keywords are lowercase
Keywords use UpperCamelCase
Keywords are ALL CAPS
Keywords can be any case
Which operator category includes the conditional operator written as condition ? expr1 : expr2 in Verilog?
Ternary operator category
Unary operator category
Binary operator category
Reduction operator category
Which literal correctly represents a 4-bit binary value equal to decimal 9?
4'b1001
9'b0100
4'h1001
'b1001
Which Boolean function does the following Karnaugh map represent?
Inclusive OR
Inclusive NOR
Exclusive OR
Exclusive NOR
An n variable K-map can have how many cells?
n^n cells
2^n cells
n^2 cells
n^2n cells
Each term in the standard SOP form is called a?
minterm
maxterm
literal
don't care
IC number of 8:1 multiplexer
74153
74138
74139
74151
Simplified expression of half adder carry is
c=xy+x
c=y+x
c=xy
c=xy+y
IC74LS139 is a
Dual 2:4 decoder
3:8Decoder
4:2 Encoder
Dual 4:1Multiplexer
