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WorksheetsCSA Unit 3
Total questions: 20
Worksheet time: 15mins
What is the role of the Control Unit in the CPU?
To perform calculations
To manage memory storage
To control the flow of data
To perform logical operations
In a simple instruction set, the instruction “MOV R1, R2” typically means:
Move data from R2 to R1
Move data from R1 to R2
Multiply R1 and R2
Add R1 and R2
Which of the following BEST describes a register?
A type of external memory
Secondary storage unit
Fast storage inside the CPU
Part of the power supply unit
What is main memory commonly called?
ROM
RAM
Cache memory
Register
Which addressing mode uses the instruction itself to specify the operand?
Immediate addressing
Direct addressing
Indirect addressing
Register addressing
What does the accumulator register do?
Stores instructions
Controls the clock speed
Holds intermediate results
Connects peripherals
Which addressing mode specifies the memory location directly in the instruction?
Immediate
Direct
Indirect
Register
What is the function of the program counter (PC) register?
Hold current instruction
Stores the output result
Point to the next instruction
Stores the input data
What does the instruction “ADD R1, #5” do in immediate addressing?
Adds contents of R1 and memory location 5
Adds 5 directly to R1
Stores 5 in the location held by R1
None of the above
Which component decodes instructions in the CPU?
ALU
Control Unit
Register
Cache Memory
The Memory Management Unit (MMU) manages:
Data transfer speeds
Multi-core processing
Memory access and storage
Interrupts
What is pipelining in CPU architecture?
Sequential processing
Error detection
Storage of data
Parallel processing
Which register indicates the status of the CPU’s condition?
Instruction register
Flag register
Accumulator
Stack pointer
What does the instruction “SUB R1, R2” typically mean in assembly language?
Store R1 in R2
Add R1 and R2
Subtract R1 from R2
Subtract R2 from R1
Which addressing mode calculates the effective address by adding the contents of a base register to a constant offset provided in the instruction?
Immediate
Indexed
Indirect
Direct
Which memory component provides the fastest data access within CPU architecture?
Level 1 Cache
DRAM
Registers
SRAM
In a system with virtual memory, the mapping from virtual addresses to physical addresses is managed by:
Cache controller
Memory Management Unit
CPU registers
DMA controller
Which addressing mode is most efficient for implementing loop counters in array processing?
Immediate addressing
Indexed addressing
Direct addressing
Register addressing
The main purpose of having separate instruction and data caches in Harvard architecture is to:
Increase register width
Prevent pipeline hazards
Simultaneous fetching
Reduce effective clock speed
What is the effect of increasing the number of pipeline stages in a CPU?
Reduced instruction throughput
Increased CPI (cycles per instruction)
Higher pipeline hazards
Simpler control logic
