WorksheetsChapter 1: Introduction - Computer Organization and Architecture
Total questions: 95
Worksheet time: 48mins
Which statement best distinguishes computer architecture from computer organization?
Organization specifies number of bits for data types
Architecture specifies control signal wiring details
Organization defines instruction set visibility to programmers
Architecture defines attributes visible to programmers
Which item is an example of a computer architecture attribute?
The timing of internal control signals
The exact interface circuitry to peripherals
The instruction set available to programs
The specific memory technology used
Which item is an example of computer organization?
The number of bits for integer data
The programmer-visible I/O mechanisms
Whether a multiply instruction exists
How interfaces to peripherals are wired
A system provides a multiply instruction. Which interpretation is correct?
Availability is an architecture attribute
Availability is an organization detail
Implementation method is an architecture attribute
Implementation method is programmer-visible
Which statements are true about code compatibility within processor families?
System/370 family members share a basic architecture
x86 family members share a basic architecture
Compatibility is at least backward within a family
Organization is identical across all family versions
Define structure versus function in computer systems.
Structure is operations; function is interconnections
Structure equals memory technology; function equals interfaces
Structure relates components; function is their operations
Structure equals visible attributes; function equals control signals
Which are the four fundamental functions of a computer?
Data movement
Data storage
Program compilation
Control
Data processing
In the functional view diagram, which component directly coordinates data movement apparatus with storage and processing units?
Central control mechanism
Operating environment controller
Arithmetic and logic unit
System interconnection hub
In the data movement operation diagram, what is the primary role of the Control element?
Execute arithmetic and logic operations
Store moved data persistently
Provide external device interfaces
Initiate movement between storage and processing
Which sequence best matches the storage operation depicted: data originates at Movement and ends at which component after Control directs it?
Storage component destination
Processing component destination
I/O subsystem destination
Registers inside CPU
In the processing-from/to-storage diagram, which path represents data being processed then written back?
Movement → Control → Processing → Storage
Control → Movement → Processing → Storage
Movement → Control → Storage → Processing
Movement → Processing → Control → Storage
Which path corresponds to processing from storage to I/O as shown in the diagram?
Movement → Control → Storage → Processing → I/O
Processing → Control → Movement → Storage
Storage → Control → Processing → Movement (I/O)
Control → Storage → Movement → Processing
Identify the four main structural components of a computer shown in the top-level structure figure.
Central processing unit (CPU)
Main memory
I/O subsystem
ALU module
Within CPU structural components, which are explicitly listed in the material?
Cache controller
Registers
Arithmetic and logic unit (ALU)
Control unit
In the top-level computer diagram, which element connects CPU, main memory, input, and output?
Control mechanism layer
Data movement apparatus
Systems interconnection
Peripheral bus matrix
In the CPU diagram, which component primarily coordinates instruction execution timing and directs data paths?
Register file collection
Arithmetic and Logic Unit
Internal CPU interconnection
Control Unit component
Which pair correctly matches a control unit sub-function with its purpose in the control unit diagram?
Control Memory: performs arithmetic operations
Registers: predict branch outcomes
Sequencing: orders micro-operations
Decoders: store control signals persistently
Which statements are true about branch prediction as a performance feature?
It selects likely instruction paths to process next
It guarantees zero mispredictions for all workloads
It is unrelated to memory access behavior
It looks ahead in fetched code to anticipate branches
What is a primary role of data flow analysis in optimizing instruction scheduling?
Detect independent instructions to avoid stalls
Convert all branches into sequential code
Replace caches with larger register files
Increase clock frequency beyond thermal limits
Which combination best supports microprocessor speed by reducing average memory access latency?
On-board L1 and L2 cache
Sequencing and decoders
Arithmetic and Logic Unit
Control memory arrays
Which statement best describes speculative execution in modern processors?
Reordering completed instructions after commit
Executing predicted branches ahead of time
Delaying loads until cache miss resolves
Prefetching entire pages into main memory
Which factor primarily causes the processor–memory performance mismatch highlighted in the figures?
Processor speed grows faster than memory speed
Memory speed grows faster than processor speed
Cache capacity shrinks over generations
I/O bandwidth increases faster than CPU speed
From the evolution graph, which pair both increased substantially over time?
Processor speed
Dynamic RAM density
Bus count
Instruction width
Dynamic RAM speed
What is a direct consequence of DRAM density increasing faster than required main memory?
Fewer DRAM chips per system over time
More DRAM chips per system over time
Unchanged DRAM chips per system count
DRAM chips per system peak then stay flat
Which trend is shown by the DRAM speed line relative to processor speed in the first figure?
DRAM speed surpasses CPU speed steadily
DRAM speed lags significantly behind CPU speed
DRAM speed oscillates around CPU speed
DRAM speed matches CPU speed closely
Why do servers and supercomputers in the second figure move to larger DRAM sizes over the years?
Processor sockets require more DIMMs physically
Workloads demand higher memory capacity
DRAM density reduces reliability of small modules
Operating systems forbid using smaller modules
Which approach increases memory throughput by widening the data path of DRAM?
Use deeper DRAM banks for tall stacks
Partition DRAM into isolated narrow lanes
Make DRAM wider to use wide bus paths
Add more refresh cycles to DRAM timing
What is the primary role of cache in improving memory performance?
Increase DRAM row activation energy
Change DRAM interface to reduce latency
Buffer I/O modules for external devices
Encrypt data stored in main memory
Which solutions specifically reduce the frequency of memory access?
More complex cache hierarchies
Cache on chip near the CPU
High speed external buses
Deeper DRAM arrays with tall stacks
Increasing interconnection bandwidth can be achieved by which methods?
Hierarchy of buses for segmented traffic
Larger caches to store entire programs
Wider DRAM banks for broad rows
High speed buses with faster signaling
Which components together constitute the Central Processing Unit (CPU)?
Control Unit and Arithmetic Logic Unit
Main Memory and I/O Module
Instruction Interpreter and Cache
General-purpose arithmetic functions
Which module handles data and instructions entering and leaving the system?
Cache module for temporal locality
ALU performing arithmetic operations
I/O module interfacing external devices
Main memory module for volatile storage
In the hardware approach diagram, how are results produced from data?
Data pass through an instruction interpreter
Data feed a sequence of arithmetic and logic functions
Data are stored in RAM then executed by software
Control signals rewire general-purpose units dynamically
In the software approach, what component translates instruction codes into control signals?
Arithmetic Logic Unit within CPU
Main memory managing program storage
Hierarchy of buses coordinating devices
Instruction interpreter for program control
What is the primary function a computer performs during normal operation?
Executing a program of stored instructions
Rendering graphics for the display
Encrypting all user data by default
Managing I/O devices continuously
Which pair correctly names the two major phases of the basic instruction cycle?
Branch and Commit
Fetch and Execute
Load and Halt
Decode and Store
During the fetch cycle, which register holds the address of the next instruction to be fetched?
Instruction Register (IR)
Program Counter (PC)
Memory Buffer Register (MBR)
Input/Output Buffer Register (I/O BR)
After an instruction is fetched, where is the instruction value placed before execution begins?
Program Counter (PC)
Execution unit cache
Memory Address Register (MAR)
Instruction Register (IR)
Which statement best describes what typically happens to the Program Counter (PC) during the fetch cycle?
It increments to point to the following instruction
It resets to zero after every instruction
It loads the fetched instruction data
It decrements to point to previous instruction
Select all components that directly participate in fetching an instruction from memory.
Program Counter (PC)
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Instruction Register (IR)
Input/Output Address Register (I/O AR)
In the state diagram of the instruction cycle, which state immediately follows 'Fetch Next Instruction' under normal operation?
Execute Instruction
Halt state
Start state
Interrupt service
Which action belongs to the processor–memory category in the execute cycle?
Transfer data between CPU and I/O module
Perform arithmetic or logical on data
Alter sequence of operations via jump
Transfer data between CPU and main memory
During the execute cycle, which set correctly pairs category with example?
Control: jump altering operation sequence
Processor–memory: change program counter only
Processor–I/O: data transfer with I/O module
Data processing: arithmetic or logical on data
In the program execution example, the PC initially contains which value and why?
300, address of the first instruction
940, address holding operand data
5941, next instruction to be fetched
1940, first instruction loaded in IR
What does the first hexadecimal digit in the IR indicate in the example?
Branch condition to evaluate
I/O device to be accessed
Memory address for operand data
Operation code specifying AC load
In the example, the remaining three hexadecimal digits in IR specify what?
Address 940 from which data are loaded
I/O module port number used
ALU function for addition
Next PC value after increment
Which registers are involved when the instruction is fetched and PC is incremented?
AC for arithmetic accumulation
MBR for data transfer buffering
MAR for memory addressing
IR to hold fetched instruction
After executing the first instruction (1940), which outcome occurs?
AC is loaded from memory address 940
PC jumps directly to address 940
ALU performs addition of two registers
I/O transfer writes to an external port
What happens immediately after fetching the next instruction 5941 in the example?
IR is pushed onto the stack for return
MBR sends data to an I/O module
AC is cleared to zero before decode
PC is incremented to point to the following instruction
Which stage typically follows instruction fetch in the instruction cycle state diagram for most architectures?
Data operation execution
Instruction address calculation
Operand store stage
I/O interrupt handling
In the instruction cycle, operand fetch is most directly required when an instruction involves which scenario?
Multiple operands from memory
Single immediate constant only
No operands, control transfer only
Operands already in program counter
Which interrupt type is commonly generated by the processor’s internal timer and used for pre-emptive multitasking?
I/O interrupt from controller
Timer interrupt for scheduling
Program interrupt from overflow
Hardware failure parity interrupt
Select all events that would raise a program interrupt.
Division by zero operation
Integer overflow during add
Memory parity hardware error
DMA controller completion
During data operation, the state diagram may return results to which destination in vector or string processing?
Operand address calculator
Return path for vector data
Program counter register
Instruction decode buffer
Which statements about I/O interrupts are accurate?
They are generated only by the internal timer
They can signal device completion or readiness
They are used exclusively for hardware failures
They originate from I/O controllers
Which step occurs first when an interrupt is detected during program execution?
Restore saved processor context
Set PC to handler address
Save current processor context
Process the interrupt routine
In the instruction cycle with interrupts, when are interrupts typically enabled for checking?
Before fetch next instruction
During execute instruction
Only at program start
After execute instruction stage
What is the immediate action taken by the CPU on an interrupt signal to transfer control?
Disable all I/O devices
Flush all pipeline stages
Set PC to interrupt handler
Jump to user program start
Which statements describe the 'disable interrupts' approach for handling multiple interrupts?
Pending interrupts are checked after current interrupt
Interrupts handled sequentially after processing
Higher priorities preempt lower priorities immediately
Processor ignores new interrupts while handling one
In a priority-based multiple interrupt system, what happens when a higher priority interrupt arrives?
It triggers a system halt for safety
It is discarded to avoid starvation
It immediately preempts the lower priority interrupt
It is queued until current interrupt finishes
Which sequence correctly outlines the control transfer via interrupts?
Set PC, restore context, execute user program
Process interrupt, save context, resume program
Save context, set PC, process, restore context
Suspend, process, save, restore context
What best defines an interconnection structure in a computer system?
A single bus connecting memory only
The paths connecting all system modules
A cache hierarchy within the CPU
A software API for device drivers
Which units require appropriate interconnections for system operation?
Central Processing Unit
Arithmetic software
Input/Output devices
Memory modules
Which signal types must a memory module handle to function within a computer system?
Instructions, cache tags, parity bits
Power, cooling, mechanical mounts
Interrupts, DMA requests, device IDs
Data, addresses, control signals
In an I/O module, what is a typical output operation from the computer’s viewpoint?
Broadcast interrupts to all devices
Generate timing for memory reads
Receive addresses from peripheral
Send data to the peripheral
Which item is explicitly listed as a control signal for memory operations?
Read and write
Parity and ECC
Refresh and precharge
Enable and chip-select
What additional role does an I/O module have beyond data transfer?
Caching instructions
Executing arithmetic
Sending interrupt signals
Allocating virtual memory
Which actions are part of a CPU module’s connection responsibilities?
Maintains peripheral firmware
Receives and acts on interrupts
Writes out processed data
Reads instructions and data
What best describes a computer bus in this context?
Communication pathway connecting devices
Power distribution rail for modules
Processor cache for temporary storage
Dedicated I/O controller for disks
Why are bus lines often described as grouped?
They are multiplexed with power rails
They exist only inside the CPU core
They share a single interrupt vector
They combine many single-bit channels
What challenge arises when many devices share one bus?
Guaranteed real-time throughput
Automatic priority inversion prevention
Increased static power dissipation only
Propagation delays and coordination issues
Which statement best characterizes the data bus at the processor-memory interface?
Carries instructions only between components
Carries data and instructions without distinction
Identifies memory source or destination addresses
Provides timing and arbitration control signals
For a system with an 8-bit, 16-bit, 32-bit, or 64-bit data bus, what primary performance factor does the width influence?
Maximum memory address capacity
Clock synchronization latency
Interrupt vector priority levels
Aggregate data transfer per cycle
What is the role of the address bus during a CPU memory access?
Buffers system bus traffic to expansion I/O
Transfers data payloads to peripherals
Indicates the memory location for read or write
Sequences DMA acknowledgments and requests
A system with a 16-bit address bus can directly address how much memory space?
64 kilobytes of addressable space
32 kilobytes of addressable space
16 kilobytes of addressable space
128 kilobytes of addressable space
Which signals are typically carried on the control bus?
I/O read and I/O write
Interrupt request and interrupt ACK
Graphic and video pixel data
Memory read and memory write
Clock and reset
When many devices share a bus, why can performance suffer?
Propagation delay for coordination increases
Cache removes all CPU-memory accesses
Aggregate transfer demand approaches bus capacity
Control signals become strictly unidirectional
Address bus width decreases automatically
In traditional hierarchical bus architecture, what is the purpose of using a cache structure connected to the local bus?
Enable serial devices to bypass the system bus
Insulate CPU from frequent main memory accesses
Reduce expansion bus connector pin count
Provide independent interrupt routing for I/O
What function does the expansion bus interface serve in a hierarchical bus design?
Arbitrates local cache transfers exclusively
Buffers traffic between system bus and I/O controllers
Generates processor clock and reset signals
Transforms address bus width dynamically
High-performance hierarchical bus architectures introduce what major enhancement?
A unified bus to remove all hierarchies
A high-speed bus for high-capacity I/O
A wider address bus for the processor
A slower bus to support legacy devices
In a high-performance hierarchy, how is the high-speed bus related to processor changes?
Disabled when cache sizes increase
Tightly coupled and changes with CPU design
Used only for serial peripheral connections
Independent of the processor architecture
Which description correctly contrasts dedicated versus multiplexed bus types?
Dedicated uses separate data and address lines
Dedicated requires a data-valid control signal
Multiplexed reduces line count but adds complexity
Multiplexed shares lines for address and data
Multiplexed guarantees ultimate performance
During bus arbitration, which statements are accurate?
CPU and DMA can both request bus control
Arbitration may be centralized or distributed
An arbiter may be part of the CPU or separate
Centralized arbitration uses multiple bus controllers
Only one module may control the bus at a time
Which statement best describes a key advantage of the PCI bus in modern computer systems?
Asynchronous timing with distributed arbitration
High-bandwidth, processor-independent peripheral interconnect
Processor-dependent design for specific CPUs
Limited to single-processor configurations only
What timing and arbitration characteristics are standard for PCI?
Asynchronous timing and shared arbitration lines
Asynchronous timing and token arbitration
Synchronous timing and centralized arbitration
Synchronous timing and decentralized arbitration
Which configuration widths are typical for PCI data paths?
8-bit or 16-bit bus widths
24-bit or 48-bit bus widths
32-bit or 64-bit bus widths
128-bit or 256-bit bus widths
Which feature contributes to PCI delivering better performance for high-speed I/O subsystems?
Support only for legacy ISA devices
High-bandwidth architecture with efficient bus protocols
Requirement of many chips to implement
Use of very low clock frequencies
Select all statements that correctly reflect the current PCI standard listed in the material.
Up to 64 data lines at 33 MHz
Requires few chips to implement
Public domain specification initially developed by Intel
Uses asynchronous timing and centralized arbitration
In a typical desktop system diagram, what is the role of the bridge/memory controller relative to the PCI bus?
Acts only as an interrupt concentrator
Acts as a data buffer between processor and PCI
Acts as a graphics-only accelerator
Acts as a direct storage controller for disks
In the typical server system diagram, how are multiple PCI configurations connected in a multiprocessor system?
Connected via graphics accelerators
Directly chained without any bridges
Connected by bridges to the system bus
Connected only through LAN controllers
Which lines are included under PCI System lines?
Interrupt request signals
Address strobe only
Error and parity signals
Clock and reset signals
What is the purpose of PCI arbitration lines according to the material?
Used only during error recovery
Time-multiplexed across address lines
Not shared, direct connection to bus arbiter
Shared among devices for fairness
Which statements about the PCI 64-bit bus extension are accurate? Select all that apply.
Adds additional 32 lines for data
Uses time multiplexing for the extension
Eliminates the need for address phases
Requires two lines to negotiate 64-bit transfers
Which sequence correctly captures major phases of a PCI transaction?
Device reset, then error phase, then parity phase
Arbiter sends interrupt, then data phase, then address phase
Master claims bus, determine transaction type, address phase, data phases
Target claims bus, then address phase, then idle
Why is AGP referred to as a port rather than a bus in this context?
It has more than four data lanes
It connects only two devices directly
It replaces PCI in all systems
It uses asynchronous timing only
