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WorksheetsIntroduction to 8085A I/O and Address Space
Total questions: 10
Worksheet time: 5mins
Which 8085A signal distinguishes whether an access targets memory or an I/O device?
RD read cycle control line
S0 status state control line
ALE latch enable control line
IO/M status selection line
When an IN instruction reads 8-bit data from an I/O port using an 8-bit port address, what is the logic level driven on the IO/M* status line during this operation?
High-impedance indicating no bus owner
Toggles between ‘0’ and ‘1’ each cycle
Logic ‘0’ indicating memory space access
Logic ‘1’ indicating I/O space access
In the diagram of a simple two-port input device, which control signal combination enables one 8-bit port to drive the processor data bus through the tri‑state buffers?
CS high and WR low with any address line
CS low and WR low with correct address line
CS high and RD low with any address line
CS low and RD low with correct address line
Which statement best describes the 8255A port organization shown in its internal architecture?
Three independent 8-bit ports with no grouping
One 8-bit port and two 12-bit multiplexed ports
One 16-bit port plus one 8-bit status port
Two 8-bit ports and one split 8-bit port
In 8255A Mode 0, what best characterizes Ports A and B?
Bidirectional 8-bit with strobed handshaking
Serial I/O with synchronous clocking
Simple 8-bit I/O without handshaking
Interrupt-driven DMA transfer capable
Which statement about handshaking in 8255A Mode 0 is correct?
Interrupt-driven handshaking is mandatory
Handshaking uses PC2–PC0 lines
Only Port A supports handshaking
No handshaking signals are used
Given base address 80H, which I/O address is used for the 8255A control register?
80H
83H
81H
82H
Reading which port provides the status word bits for Mode 1 handshaking in the 8255A?
Port A data register
Port C status register
Control word register
Port B data register
Which pair best represents the Mode 1 output handshaking signals between 8255A and a printer on Port A?
OBF from 8255A, ACK from peripheral
ACK from 8255A, OBF from peripheral
WR from printer, INTR from printer
IBF from 8255A, OBF from printer
During Mode 1 output, the CPU writes data to Port A. Which immediate effect on the status lines is expected?
INTR becomes active indicating service
ACK becomes active indicating data taken
IBF becomes active indicating input full
OBF becomes active indicating data available
