WorksheetsPage 1
Total questions: 80
Worksheet time: 40mins
According to the Logical Synthesis Flow, which step immediately follows "Parsing HDL"?
Mapping into a standard cell library
Logic Optimization (Technology Independent)
Technology dependent optimization
Place and Route
In the context of Logic Optimization, what is the primary goal of transforming equations?
To map them directly to standard cells
To reduce the number of transistors to zero
To transform equations to Boolean equations and perform reduction
To fix hold time violations
Which of the following is considered a "Technology Dependent" step in the synthesis flow?
Two-level logic reduction
Multi-level logic optimization
Mapping into a standard cell library
Parsing HDL
During "Technology dependent optimization", which action is performed to reduce load on critical nets?
Two-level logic reduction
Buffer insertion or cloning
Functional block synthesis
Mathematical operator optimization
How is the area of logic gates and interconnects approximated during cost estimation?
By the number of logic levels
By the number of transistors, which is approximated by the number of literals
By the number of input pins only
By the total power consumption
In cost estimation, the critical path delay is approximated by which metric?
The number of literals
The maximum number of logic levels (logic depth)
The fanout of the output net
The clock frequency
For the sum-of-products expression f=abc+b′c+ca+b′ , what is the estimated Area and Delay based on the slides' example?
Area = 4, Delay = 4
Area = 8, Delay = 2
Area = 6, Delay = 3
Area = 2, Delay = 8
Which verification method is described as dividing GL verification into two fast steps for large designs?
Dynamic Simulation and FPGA Emulation
Formal Verification and Static Timing Analysis (STA)
BIST and Boundary Scan
Manual Inspection and OVM
Why is FPGA or emulation stated as unsuitable for the specific GL verification mentioned in the slides?
They cannot handle Verilog code
They are too expensive compared to testers
The slides explicitly state "Cannot use FPGA or emulation for such verification"
They do not support clock gating
What does Formal Verification prove regarding two designs?
That they have valid timing paths
That they are logically equivalent in structure and functionality
That they consume the same amount of power
That they have the same layout footprint
Which of the following does Static Timing Analysis (STA) explicitly NOT check?
Timing violations
Propagation delay along paths
Input/output interface timing
Functionality of the design
According to the slides, what is the cost of a 1000-pin tester?
$100-200 thousand
$500 thousand
$2-3 millions
$10 millions
Which of the following is NOT listed as one of the three test strategies?
Scan-test
Built-in self test (BIST)
Boundary scan test
Manual voltage probing
The "Stuck-At (SA) Fault Model" assumes failures cause nodes to be:
Floating or high impedance
Shorted to GND (stuck-at 0) or VDD (stuck-at 1)
Delaying the signal by 50%
Oscillating between 0 and 1
What constitutes a "Test Vector" or "Test Pattern"?
The forced input only
The correct output only
The forced input as well as the correct outputs
The list of all faults in the design
What is the primary trade-off mentioned for achieving "Complete coverage"?
It requires no test vectors
It leads to a large number of vectors and high test cost
It reduces the need for DFT
It increases the chip speed
For a complex design, what is the typical test coverage settled for?
50%
75%
90+%
100%
In the NOR2 gate example, how many total Stuck-At (SA) faults are there?
3
4
6
8
In the NOR2 gate example, the faults detected by a '00' input pattern are considered:
Dominant
Equivalent
Redundant
Undetectable
According to the principle of "Dominance" in the NOR2 example, which fault dominates a/0 and b/0?
z/0
z/1
a/1
b/1
Which input pattern detects the b/0 fault in a NOR2 gate?
00
01
10
11
What is the minimum set of patterns required to detect all faults in the NOR2 example?
00, 11
00, 01, 10
01, 10, 11
00, 01, 10, 11
"Controllability" is defined as the ability to:
Test an internal node by watching external outputs
Force an internal node by driving inputs
Measure the delay of a path
Repair a defect automatically
"Observability" is defined as the ability to:
Test an internal node by watching external outputs
Force an internal node by driving inputs
View the chip under a microscope
Control the clock frequency
How are Flip-Flops (FFs) modified to create a scan chain?
By removing the clock input
By converting them into scan-FFs with 2 inputs using a MUX
By replacing them with latches
By connecting them all to VDD
In a scan-FF, what does the "Normal mode" (Scan=0) MUX selection correspond to?
The scan-in (SI) input
The D input
The Q output inverted
The clock input
In "Scan mode" (Scan=1), the MUXs select the SI input to form a:
Shift register
Parallel load register
Counter
ROM
During the "Shift" operation in a scan chain, what happens?
SCAN is de-asserted
Input pattern is loaded serially to all FFs from scan-in
D-inputs are stored in Qs
Logic blocks produce outputs
During the "Capture" operation, what occurs?
SCAN is asserted
Result is read serially from scan-out
SCAN is de-asserted (Normal Mode) and logic block outputs are stored in FFs
The clock is stopped
How many clock cycles are needed to load an input pattern serially into an 8-FF scan chain?
1
4
8
16
Can the loading of a new input pattern and the reading of results from scan-out happen simultaneously?
No, they must be separate steps
Yes, simultaneously load new input while reading results
Only if the chain is less than 4 FFs
Only in capture mode
What is the primary benefit of dividing a scan chain into N parallel chains?
It increases the fault coverage
It reduces (divides) shift time by a factor of N
It reduces the number of pins required
It eliminates the need for ATPG
What is the "cost" associated with using parallel scan chains?
Increased shift time
Increased pin count by 2(N-1) pins
Reduced clock speed
Lower test coverage
Test Compression is used primarily to:
Increase the number of FFs
Save pin count
Slow down the testing process
Eliminate the need for ATE
Where is the decompression of the stimulus performed in a test compression architecture?
On the ATE software only
Inside the core logic
On-chip, before the scan chains
On-chip, after the scan chains
Why is scan chain insertion usually done after synthesis?
Because scan-FFs have no delay
Because scan-FFs have different delays compared to normal FFs, requiring timing analysis/fixing
Because HDL parsing cannot handle scan-FFs
Because it is illegal to do it during synthesis
Built-In Self-Test (BIST) generates patterns using:
An external pattern generator
A Pattern Generator creating pseudo-random test patterns on-chip
Manual dip switches
A stored ROM table off-chip
In BIST, the "Signature Analyzer" performs what function?
Generates the clock signal
Combines multiple outputs into a signature (syndrome)
Resets the circuit
Fixes the faults found
Which of the following is listed as a "Con" (disadvantage) of BIST?
Slow testing
Increased testing ports
Area overhead and added complexity
High testing cost
Scan BIST combines scan test with BIST using which components?
FPGA and CPLD
PRSG & BILBO
ALU and MAC
PLL and DLL
Boundary Scan (BS) was developed to address defects at which level?
Transistor level
Gate level
Board level (traces & solder joints)
Operating System level
How are Boundary Scan cells configured?
They replace the core logic entirely
They are inserted at the pins and cascaded to form a BS chain
They are placed only on power pins
They are used for memory testing only
Which of the following is NOT a capability of a BS cell?
Force value on pin
Capture data from pin
Capture data from core logic
Repair solder joints automatically
To test PCB connections between chips using Boundary Scan, values are shifted into the driving chip's outputs and compared with:
The values shifted out from the driven chip's inputs
The core logic of the driving chip
The power supply voltage
The extracted netlist
What is the standard number of pins used for the JTAG (IEEE 1149.1) interface?
2
3
5
8
Which pin in the JTAG interface is optional?
TCK
TMS
TRST*
TDI
In the Scan Chains Simulation Testbench, a third DUT is instantiated for:
The original RTL
The GL netlist with DFT (GL+DFT)
The test pattern generator
The analog phy
When test=1 in the scan simulation testbench, the goal is to:
Verify normal operation
Verify scan chains operation by scan-in/scan-out checks
Check power consumption
Reset the design
According to the slides, what is the approximate number of scan channels on a typical tester?
1-5
10-200
1000-2000
10000+
The "Stuck-At" fault model is described as:
Perfectly accurate physically
Not quite true, but works well in practice
Only applicable to analog circuits
Obsolete and unused
"Equivalence" in fault modeling means that faults are:
Indistinguishable at the output
Located on the same wire
Always 1
Causing short circuits
In Logic Optimization (Technology Independent), one of the steps is:
Library binding
Resize cells
Two-level logic reduction
Fanout restructuring
High-level optimization of mathematical operators generally happens during:
Parsing HDL
Mapping into a standard cell library
Technology dependent optimization
Post-synthesis verification
If a design has a logic depth of 10, this metric is used to estimate:
Area
Critical path delay
Power
Test coverage
Formal verification validates "GL netlist against RTL" typically after:
Layout placement
Synthesis and DFT insertion
Fabrication
Packaging
The limitation of BIST regarding observability is due to:
Output compression
Lack of clock speed
Too many test ports
Pseudo-random patterns being perfect
Which standard defines the Test Access Port (TAP)?
IEEE 802.11
IEEE 1149.1
IEEE 754
IEEE 1800
In the context of "Parallel Scan Chains", if N=4, the shift time is reduced by a factor of:
2
4
8
16
The component "ATE" stands for:
Automatic Test Equipment
Advanced Timing Estimation
Analog Test Environment
Algorithmic Test Engineering
Which of the following is a capability of "Test Compression"?
It allows using testers with fewer scan channels to test chips with many chains
It eliminates the need for scan chains
It compresses the silicon area
It reduces the clock frequency needed
Boundary Scan testing of "through-hole tech" historically used:
Floating pins tester
Bed-of-nail tester
X-ray inspection
Visual checking
The logic equivalence checking in Formal Verification compares the structure and functionality without:
Mathematical methods
Dynamic simulation / testbench development
Knowing the RTL
Any constraints
Which flow step includes "Fanin/Fanout restructuring"?
Parsing HDL
Logic Optimization
Technology dependent optimization
Mapping
Area estimation by "number of literals" assumes:
Area is proportional to number of transistors
Area is proportional to clock speed
Area is proportional to number of pins
Literals are always zero
A "single test vector" can possibly check:
Only one node
Multiple nodes
Only power pins
Only the clock signal
In the "Shift" phase of scan testing, the Scan signal is:
0 (Normal Mode)
1 (Scan Mode)
High Impedance
Clocked
In the "Capture" phase of scan testing, the Scan signal is:
0 (De-asserted)
1 (Asserted)
Undefined
Negative
The "Dominance" relationship helps to:
Increase the number of faults
Reduce the number of test vectors by identifying faults that are detected by tests for other faults
Physically merge wires
Increase power
In Scan BIST, "PRSG" stands for (inferred context):
Pseudo-Random Sequence Generator
Parallel Register Shift Group
Programmable Read Scan Group
Physical Region Scan Grid
"Scan-FFs" have 2 inputs. They are:
D and Q
D and SI (Scan-in)
Set and Reset
Clock and Enable
When using Boundary Scan to test the board, the chain spans:
Only one chip
The entire board (all chips cascaded)
Only the processor
Only the memory
The 5 pins of JTAG (TCK, TMS, TDI, TDO, TRST) allow access to:
Only Boundary Scan registers
Boundary Scan and internal Scan Chains/BIST
The power grid only
The external oscillator only
Why do some tools perform scan chain insertion during synthesis?
To avoid using MUXes
To consider scan-FF timing from the start
To reduce the number of literals
To skip ATPG
"BIST" stands for:
Board Integrated System Test
Built-In Self-Test
Basic Internal Scan Test
Binary Input Shift Test
What is the value of the "Error Status" in a BIST system?
A 32-bit code
Simply PASS / FAIL
A waveform
A delay value
In the Logical Synthesis flow, "Buffer or clone to reduce load on critical nets" is part of:
Logic Optimization
Mapping
Technology dependent optimization
Parsing
"Logic depth" is used to estimate:
Area
Delay
Power
Yield
Which test strategy involves "Result from chains scan-out (response) is compressed"?
Standard Scan
Test Compression
Boundary Scan
Manual Test
The phrase "Defects & process variations in fabrication affects functionality & performance" is the primary reason for:
Synthesis
Testing of Integrated Circuits
Parsing HDL
Layout
A 1000-pin tester cost is cited to demonstrate:
Why we should buy more testers
Why we must minimize test time
Why we need 2000 pins
Why fabrication is cheap
