WorksheetsAPR MCQ Exam — Automatic Placement & Routing
Total questions: 83
Worksheet time: 42mins
Select the best answer for each question. No external materials allowed. According to the General Physical Synthesis Flow, what is the first step?
Placement
Routing
Floorplanning
Clock Tree Synthesis
Select the best answer for each question. No external materials allowed. Which of the following correctly describes the steps of Routing in the General Physical Synthesis Flow?
Global routing followed by Detailed routing
Detailed routing followed by Global routing
Power routing followed by Signal routing
Clock routing followed by Data routing
Select the best answer for each question. No external materials allowed. What is the primary function of Floorplanning?
To arrange standard cells within a block
To determine sizes and locations of all blocks
To connect all nets by metal interconnects
To perform DRV and LVS checks
Select the best answer for each question. No external materials allowed. Which of the following is an explicit INPUT to the Floorplanning step?
Parasitic extraction file
Final layout with wiring
Hierarchical structural netlist used cells and connections
GDSII file
Select the best answer for each question. No external materials allowed. In Floorplanning, chip size constraints are used to ensure the design fits in the:
Test bench
Package cavity
Wafer scribe line
Reticle limit
Select the best answer for each question. No external materials allowed. Which of the following is an OUTPUT of the Floorplanning process?
Detailed transistor layout
Decide blocks size & location
Final metal routing paths
Post-layout simulation results
Select the best answer for each question. No external materials allowed. In the Floorplanning phase, which decision is marked as "Optional" in the slides?
Decide location of I/O pads
Decide routing areas (channel assignment)
Decide location of power pads
Decide blocks size
Select the best answer for each question. No external materials allowed. The Floorplanning phase decides the location and style of distribution for which two critical signal types?
Power and Clock
Reset and Enable
Data and Control
Scan and Test
Select the best answer for each question. No external materials allowed. What is the main Optimization goal during Floorplanning?
Optimize overall chip area while minimize routing lengths
Optimize transistor switching speed
Minimize number of I/O pads
Minimize manufacturing yield loss
Select the best answer for each question. No external materials allowed. Floorplanning involves applying an algorithm to optimize block location, orientation, and:
Transistor sizing
Aspect-ratio and pin locations
Metal layer thickness
Oxide capacitance
Select the best answer for each question. No external materials allowed. Which of the following is classified as a "Fixed block" or "Hard IP" during floorplanning?
Standard cells
Flexible blocks
Analog blocks and memories
Unplaced logic gates
Select the best answer for each question. No external materials allowed. Flexible blocks (Soft IPs) are characterized by being:
Built from standard cells and not yet placed
Fully routed and hardened
Analog components with fixed geometry
External chips on the PCB
Select the best answer for each question. No external materials allowed. For Flexible blocks (Soft IPs), which properties are adjustable during placement?
Transistor threshold voltages
Aspect-ratio and pin-locations
Supply voltage levels
Metal layer count
Select the best answer for each question. No external materials allowed. Which signal nets need "special attention" during Floorplanning?
Data bus nets
Power supply and clock signal nets
Scan chain nets
GPIO control nets
Select the best answer for each question. No external materials allowed. According to the slides, what is performed as part of Floorplanning regarding power/clock?
Sizing and final topology
Architecture and structure
Detailed routing
Parasitic extraction
Select the best answer for each question. No external materials allowed. The Clock distribution should be designed to minimize:
Skew & jitter
Resistance & capacitance only
Blockage & congestion
Area & leakage
Select the best answer for each question. No external materials allowed. Which phenomenon causes IR drop in the supply?
Wire inductance
Wire resistance
Gate capacitance
Subthreshold leakage
Select the best answer for each question. No external materials allowed. Which phenomenon causes Inductive drop in the supply?
Wire resistance
Wire capacitance
Wire inductance
Dielectric breakdown
Select the best answer for each question. No external materials allowed. What does the Power distribution network add to minimize IR drop?
Pad capacitors
Rings & straps
Level shifters
Clock buffers
What does the Power distribution network add to minimize Inductive drop?
Rings & straps
Pad capacitors
Ferrite beads
Voltage regulators
What is the main function of Placement?
Define the core boundary
Arrange all cells within a flexible block
Create metal interconnects for all nets
Verify design rules
Which of the following is an INPUT to the Placement step?
Layout of block without routing
Structural netlist of block
Detailed routing instructions
Extracted netlist
Which of the following is an OUTPUT of the Placement step?
Structural netlist of block
Block size constraints
Layout of block without routing
Synthesized gate-level netlist
What is a primary Optimization goal during Placement?
Optimize area while minimize routing lengths
Minimize number of transistors
Maximize clock frequency only
Minimize fabrication cost
Placement optimization must meet timing constraints for:
All nets
Critical nets
Power nets only
Clock nets only
Which Placement optimization is listed as "Optional" in the slides?
Area optimization
Routing length minimization
Timing constraint satisfaction
Optimize power & cross talk
According to Cell Layout Rules, cells are made to be:
Separated by guard rings
Abutted
Overlapped
Rotated 45 degrees
In Cell Layout Rules, cells must have:
Same width, variable height
Same height, variable width
Same height, same width
Variable height, variable width
How do cells in a row share power connections?
They share Vss/Vdd
They use separate power wires
They use external jumpers
They connect to a central bus only
What is the benefit of Mirrored top & bottom Rows?
Shared Clock lines
Shared Input pins
Shared Vdd and Vss
Reduced cell height
For routing INSIDE all cells, the layout uses:
Only limited layers
All available metal layers
Only the top metal layer
Only polysilicon
High layers are used by the router to:
Create transistors
Connect signals over the cells
Form the substrate body
Create local interconnects
In the Example: Cell Layout Rules, what is the Cell Height?
24 lambda
50 lambda
6 lambda
100 lambda
In the Example: Cell Layout Rules, the Cell Width must be multiples of:
2 lambda
5 lambda
6 lambda
10 lambda
In the Example: Cell Layout Rules, what is the width of VDD and VSS?
5 lambda
10 lambda
6 lambda
24 lambda
In the Example: Cell Layout Rules, what is the NWELL Height?
50 lambda
6 lambda
24 lambda
12 lambda
How much of the NWELL is outside the abutment box in the example?
0 lambda
1 lambda
5 lambda
6 lambda
According to the slides, what is the Virtual Machine Path for all cells (.ap)?
/home/user/design/cells
/usr/bin/cadence/cells
/usr/lib/alliance/cells
/etc/vlsi/library
What is the main definition of Routing?
Arranging cells in rows
Connect all nets by metal interconnects
Verifying geometric rules
Extracting parasitic capacitance
Global Routing is responsible for:
Performing metal interconnection of all nets
Optimize routing paths for all nets
Manufacturing the masks
Placing I/O pads
Detailed Routing is responsible for:
Optimizing block locations
Optimizing routing paths only
Performs metal interconnection of all nets
System-level partitioning
During Global Routing, how are possible congestions solved?
By adding more metal layers
Can move cells/rows to make room for interconnections
By decreasing the clock frequency
By increasing chip size
Which of the following are the Inputs for Global Routing?
Chip floorplan and Placement information
GDSII file and Tech file
Netlist and Constraints only
Extracted netlist and Delays
What is the Output of Global Routing?
Final GDSII file
List of DRC violations
Instructions to detailed router how to route every net
Placed standard cells
What is an Optimization goal of Global Routing?
Minimize routing length especially for critical path
Minimize cell density
Maximize voltage swing
Minimize latch-up risk
Detailed Router creates:
Global routing guides
Metal interconnects for all nets
Floorplan regions
Clock tree buffers
How does Detailed Routing optimize delay?
By increasing wire width
By decreasing voltage
By moving blocks
By adding repeaters
Which optimization in Detailed Routing is marked as "Optional" in the slides?
Minimize overlap/coupling capacitance
Optimize wire width
Metal interconnection
Delay reduction
Which of the following describes the Inputs to Detailed Routing?
Gate-level netlist only
Global routing instructions, Chip floorplan, and Placement information
Final layout only
Test vectors
What is the Output of Detailed Routing?
Global routing plan
Final layout including all wiring
Pre-layout simulation report
Timing constraints file
Which command is shown in the slides for Example: Routing Layout?
$ routing -start
$ graal -l filename
$ place_and_route
$ magic -exclude
What does LVS (Layout vs. Schematic) check?
Checks layout against geometric rules
Checks layout devices and connectivity have one-to-one correspondence with gate-level netlist
Checks layout against electrical rules
Checks timing violations
What does DRC (Design Rules Check) check?
Checks layout against geometric rules
Checks connectivity
Checks electrical rules
Checks logic functionality
What does ERC (Electric Rules Check) check?
Checks layout against geometric rules
Checks layout devices
Checks layout against electrical rules
Checks antenna effects
In the Physical Verification flow diagram, what is compared against the Extracted Netlist?
Layout
Gate-level netlist (Schematic)
GDSII
Simulation Waveforms
Why is Parasitics Extraction / Post-Layout Simulation necessary?
Because logic synthesis provides perfect delays
Because adding wires have big impact on delays & circuit performance
Because placement & routing do not estimate wire length
Because standard cells have no delay
What does Parasitics Extraction (PEX) generate?
Final GDSII
Extracted netlist including interconnect parasitics
Behavioral VHDL
Standard cell library
What is the function of Delay Back-Annotation?
Generates delays based on parasitics and replaces them in the extracted netlist
Removes delays from the netlist
Synthesizes the clock tree
Performs formal verification
What does Post-layout Simulation check?
Logic functionality without delays
Performance of the extracted netlist with delays
Geometric design rules
Power consumption only
In the General Chip Integration Flow, what is the first step?
Global power distribution
Adding pads
Global clock distribution
Chip physical verification
In the General Chip Integration Flow, what comes immediately after Adding pads?
Tape-out
Chip physical verification
Global power distribution
GDS generation
In the General Chip Integration Flow, what is step 3?
Global clock distribution
Adding pads
Tape-out
DRC
In the General Chip Integration Flow, what is step 4?
GDS generation
Chip physical verification
Global power distribution
Adding pads
What is the final step (Step 5) of the Chip Integration Flow?
Adding pads
Global clock distribution
GDS generation (Tape-out)
Netlist extraction
According to the Pad Frame example, pads use level shifters to standard external supplies of:
5V/12V
1.0V/0.8V
220V
3.3V/2.5V/1.8V
The chip must have which two supplies?
Internal (core) supply & External (pad) supply
Digital supply & Analog supply only
High voltage & Low voltage only
AC & DC supply
Pad rings are continuous metal rings connected by abutment. What is used for continuity at corners?
Jumper wires
Corner cell
Via arrays
Wire bonds
What does an Input pad contain?
Cascaded buffer
PLL
ESD protection, clamps, level-shifter, resistor
Clock divider
What does an Output pad contain?
ESD protection only
Level-shifter, cascaded buffer to drive large load
Sense amplifier
ADC
Why are multiple distributed supply pads used?
To increase resistance
To reduce overall series inductance
To increase chip area
To look symmetric
Why are VDD and GND pads placed next to each other?
To reduce overall inductance
To increase capacitance
To simplify bonding
To avoid short circuits
Where are Power rings placed in the Power Distribution Strategy?
Inside the core
Around the core to have multiple access points
Only at the corners
Outside the pad frame
How are Power rings connected?
To corresponding pads
To each other only
To the substrate only
To clock lines
Does the Clock pad have an internal access to the core?
Yes, direct access
No, it does not have an internal access to core
Only in 5nm technology
Depends on the frequency
Where is a clock ring formed?
In the core center
In the padframe when all pads are placed
On the PCB
In the package
How is the clock signal delivered to the core if the Clock pad has no internal access?
Through the substrate
Power pads have versions with clock buffers and core access
Wireless transmission
Through the scribe lines
For large cores, what is suggested regarding clock access?
Use only one access point
Can use multiple core access
Remove the clock ring
Use a slower clock
In the Clock Distribution Strategy diagram, what does `vdde` represent?
VDD_core
VDD_pad
VSS_core
Clock input
In the Clock Distribution Strategy diagram, what does `vssi` represent?
VSS_pad
VDD_pad
VSS_core
Clock output
What is the format of the Structural VHDL file mentioned in Chip Netlist?
.vst
.vhd
.v
.txt
To know pad cell pins, one should open the pad (.vbe) in which path?
/usr/local/bin
/home/cadence/lib
/usr/lib/alliance/cells/padlib
/etc/cells
In addition to common pins, the `pvssick_sp` pad has which specific pin?
reset
cko (clock, must be connected to core)
scan_en
test_mode
Regarding the netlist note: Power supplies vdd, vss, vdde, and vsse are:
Not connected in pads
Connected in all pads, but not shown in this netlist
Shown explicitly in every line
Not used in this design
