WorksheetsAnalog IC Design Course Syllabus
Total questions: 10
Worksheet time: 5mins
Which unit focuses primarily on MOS device physics and amplifier configurations such as CS, CG, and Source Follower with active loads?
Unit II emphasizes feedback and compensation topics
Unit IV emphasizes multipole systems and phase margin
Unit III emphasizes logic faults and scan testing
Unit I emphasizes MOS physics and configurations
In the context of amplifier design targets, which performance set is explicitly listed: SR, noise, gain, BW, ICMR, power dissipation, voltage swing, and high‑gain structures?
Design specifications for differential and cascode amplifiers
Layout rules for parasitic capacitance extraction
Packaging constraints for thermal and mechanical limits
Digital timing margins for synchronous sequential logic
Which topic explicitly addresses the Miller effect and association of poles with nodes in frequency response?
Unit II on frequency response of CS, CG, and followers
Unit I on folded cascode active‑load stages
Unit IV on slew rate in two‑stage op‑amps
Unit V on level‑sensitive scan design
Noise is treated in several contexts. Which grouping correctly lists noise topics covered?
Noise in operational amplifiers
Noise in single‑stage amplifiers
Noise in differential amplifiers
Noise in digital clock distribution
Which unit concentrates on properties and types of negative feedback circuits and effects of loading in feedback networks?
Unit IV on frequency compensation methods
Unit I on MOS models and configurations
Unit III on operational amplifier performance
Unit V on fault detection techniques
Operational amplifier coverage includes which combination of topics?
Single‑stage and two‑stage op‑amps
Scanning path optimization in logic
Input range limits and gain boosting
Slew rate and power supply rejection
Frequency compensation is treated along with which stability metric and architecture context?
Loop bandwidth and ring oscillators
Phase margin and two‑stage op‑amps
Noise factor and common‑gate mixers
Damping ratio and Schmitt triggers
Which topics are explicitly listed under design for testability in logic circuits?
Built‑in self‑test mechanisms
Partial scan methodologies
Level‑sensitive scan design
Ad hoc test techniques
Which unit would most directly cover the association of poles with nodes when analyzing amplifier frequency response?
Unit II covering CS, CG, follower stages
Unit I covering MOS models and loads
Unit III covering negative feedback types
Unit V covering scan and self‑test
Which amplifier configurations are explicitly included with active loads in the syllabus?
Source Follower and Differential pair
Cascode and Folded Cascode
Common Source and Common Gate
Emitter follower and Darlington pair
