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Worksheets

Page 1

Total questions: 36

Worksheet time: 18mins

Name
Class
Date
1.

What is computer architecture?

a)

set of categories and methods that specify the functioning, organisation, and implementation of computer systems

b)

set of principles and methods that specify the functioning, organisation, and implementation of computer systems

c)

set of functions and methods that specify the functioning, organisation, and implementation of computer systems

d)

None of the mentioned

2.

What is computer organization?

a)

structure and behaviour of a computer system as observed by the user

b)

structure of a computer system as observed by the developer

c)

structure and behaviour of a computer system as observed by the developer

d)

All of the mentioned

3.

Which of the following is a type of computer architecture?

a)

Microarchitecture

b)

Harvard Architecture

c)

Von-Neumann Architecture

d)

All of the mentioned

4.

Which of the following is a type of architecture used in the computers nowadays?

a)

Microarchitecture

b)

Harvard Architecture

c)

Von-Neumann Architecture

d)

System Design

5.

Which of the following is the subcategories of computer architecture?

a)

Microarchitecture

b)

Instruction set architecture

c)

Systems design

d)

All of the mentioned

6.

Which of the architecture is power efficient?

a)

RISC

b)

ISA

c)

IANA

d)

CISC

7.

What does CSA stands for?

a)

Computer Service Architecture

b)

Computer Speed Addition

c)

Carry Save Addition

d)

None of the mentioned

8.

If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have ______

a)

Generation word

b)

Exception handling

c)

Imprecise exceptions

d)

None of the mentioned

9.

To reduce the memory access time we generally make use of ______

a)

SDRAMs

b)

Heaps

c)

Caches

d)

Higher capacity RAMs

10.

The IA-32 system follows which of the following design?

a)

CISC

b)

SIMD

c)

RISC

d)

None of the mentioned

11.

Which of the following architecture is suitable for a wide range of data types?

a)

IA-32

b)

ARM

c)

ASUS firebird

d)

68000

12.

In IA-32 architecture along with the general flags, which of the following conditional flags are provided?

a)

TF

b)

IOPL

c)

IF

d)

All of the mentioned

13.

The VLIW architecture follows which approach to achieve parallelism?

a)

SISD

b)

MIMD

c)

MISD

d)

SIMD

14.

What does VLIW stands for?

a)

Very Long Instruction Width

b)

Very Large Instruction Word

c)

Very Long Instruction Width

d)

Very Long Instruction Word

15.

In CISC architecture most of the complex instructions are stored in _____.

a)

CMOS

b)

Register

c)

Transistors

d)

Diodes

16.

Both the CISC and RISC architectures have been developed to reduce the ______

a)

Time delay

b)

Semantic gap

c)

Cost

d)

All of the mentioned

17.

_______ are the different type/s of generating control signals.

a)

Hardwired

b)

Micro-instruction

c)

Micro-programmed

d)

Both Micro-programmed and Hardwired

18.

If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).

a)

2

b)

~1

c)

~7

d)

2

19.

The small extremely fast, RAM's all called as ________

a)

Heaps

b)

Accumulators

c)

Stacks

d)

Cache

20.

For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?

a)

ANSA

b)

Super-scalar

c)

ISA

d)

All of the mentioned

21.

What is the full form of ISA?

a)

Industry Standard Architecture

b)

International Standard Architecture

c)

International American Standard

d)

None of the mentioned

22.

Which of the following is the fullform of CISC?

a)

Complex Instruction Sequential Compilation

b)

Complete Instruction Sequential Compilation

c)

Computer Integrated Sequential Compiler

d)

Complex Instruction Set Computer

23.

The reason for the cells to lose their state over time is ________

a)

Use of Shift registers

b)

The lower voltage levels

c)

Usage of capacitors to store the charge

d)

None of the mentioned

24.

In order to read multiple bytes of a row at the same time, we make use of ______

a)

Memory extension

b)

Cache

c)

Shift register

d)

Latch

25.

The difference in the address and data connection between DRAM’s and SDRAM’s is ______

a)

The requirement of more address lines in SDRAM’s

b)

The usage of a buffer in SDRAM’s

c)

The usage of more number of pins in SDRAM’s

d)

None of the mentioned

26.

The chip can be disabled or cut off from an external connection using

a)

ACPT

b)

RESET

c)

LOCK

d)

Chip select

27.

The controller multiplexes the addresses after getting the signal

a)

INTR

b)

ACK

c)

RESET

d)

Request

28.

The data is transferred over the RAMBUS as

a)

Blocks

b)

Swing voltages

c)

Bits

d)

Packets

29.

The memory devices which are similar to EEPROM but differ in the cost effectiveness is

a)

CMOS

b)

Memory sticks

c)

Blue-ray devices

d)

Flash memory

30.

The flash memory modules designed to replace the functioning of a hard disk is

a)

RIMM

b)

FIMM

c)

Flash drives

d)

DIMM

31.

In a 4K-bit chip organisation has a total of 19 external connections, then it has ______ address if 8 data lines are there.

a)

10

b)

12

c)

9

d)

8

32.

What does ISO stands for?

a)

International Software Organisation

b)

Industrial Software Organisation

c)

International Standards Organisation

d)

Industrial Standards Organisation

33.

The bit used to signify that the cache location is updated is _________

a)

Flag bit

b)

Reference bit

c)

Update bit

d)

Dirty bit

34.

During a write operation if the required block is not present in the cache then ______ occurs.

a)

Write miss

b)

Write latency

c)

Write hit

d)

Write delay

35.

The bit used to indicate whether the block was recently used or not is ______

a)

Reference bit

b)

Dirty bit

c)

Control bit

d)

Idol bit

36.

The number successful accesses to memory stated as a fraction is called as _____

a)

Access rate

b)

Success rate

c)

Hit rate

d)

Miss rate