Pasha Flashcard Computing

Front

Which of these is not an assembly code mnemonic: ADD, STA, HLT, DAT?

Back

BRN

Front

What does the POST do ?

Back

send signals to all cpu components checking they are there and letting the cpu know they exist

Front

What is Vonn neumann archictecture?

Back

Shared memory space for instructions and data and only one bus.

Front

The CIR holds the _______ instruction being executed divided in the ________ and ________

Back

current opcode operand

Front

Which is the correct version for the levels of CACHE ? L1 is the fastest but small. Level 2 is slower but bigger. And level 3 is slower but bigger. 
, L1 is the slowest but big. Level 2 is faster but smaller. Level 3 is faster and smaller. , There are no levels of cache, L3 is the fastest but smallest. L2 is faster but bigger. Level 1 is faster and even more small

Back

L1 is the fastest but small. Level 2 is slower but bigger. And level 3 is slower but bigger.