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ATS 2024: Track 2

ATS 2024: Track 2

Assessment

Presentation

English

1st - 5th Grade

Practice Problem

Medium

CCSS
6.NS.B.3, HSN.VM.C.6

Standards-aligned

Created by

Bhanu Prakash

Used 4+ times

FREE Resource

1 Slide • 10 Questions

1

ATS 2024:
Track 2

2

Multiple Choice

Paper: Improving PreHVS Sidd Yield Loss via Optimization of GIDL-Related Process Parameters in 3nm

Question: Which leakage component is dominant at high voltage presented in this work?

1

Isub-th

2

Igidl

3

Ijunction

4

Itunnel

3

Multiple Choice

Paper: 7nm Versal Automotive Qualification & Enablement

Question: How many Versal AI Edge devices offer for Automotive?

1

5

2

6

3

7

4

8

4

Multiple Choice

Paper: Legacy Resurgence: Framework For Achieving Vertical Revenue Take-Off

Question: Choose the 2 correct manufacturing flow optimization with speed prediction

1

FT2 Skip and Increase Upfront Marking

2

Backend Marking Skip and FT2 test time reduction

3

FT2 Skip and FT2 test time reduction

4

FT2 Skip and Backend Marking Skip

5

Multiple Choice

Paper: OBP PRISM DPPM Improvement

Question: What does PRISM stand for?

1

Precision, Reliability, Inclusivity, Systematic, Minimally

2

Precision, Robust, Innovative, Systematic, Minimally

3

Precision, Reliability, Innovative, Systematic, Minimally

4

Power, Reliability, Innovative, Systematic, Minimally

6

Multiple Choice

Paper: Giga-Transceiver Functional Pattern Test-Time Reduction (TTR)

Question: In Production screen, what is the approximated optimized wait time for RX CDR to settle after attribute configuration?

1

50ms

2

100ms

3

200ms

4

300ms

7

Multiple Choice

Paper: 7nm IP Block Defect Density Normalization and Implementation for Silicon Yield Improvement

Question: Name the Defect Density Model used for Block DD Computation

1

Murphy model

2

Bose Einstein Model

3

Poisson Model

4

None of the above

8

Multiple Choice

Paper: SCAN Yield Improvement for AI Chip by Optimizing SRAM RM Timing

Question: Which RM settings implemented for Scan VMAX test?

1

000

2

001

3

101

4

111

9

Multiple Choice

Paper: Ameliorating Pre & Post Silicon Validation Methods for Multi-Die Packages with Multi JTAG Interfaces

Question: In Salina 375, Which die is assigned as the Master TAP?

1

Die 0

2

Die 1

3

No designated master die

4

Die with address strap 0x00D

10

Multiple Choice

Paper: Next-Generation Automotive Solutions: Enabling 7nm WS at 125°C

Question: What strategy was applied in this paper?

1

Shift Right Moving in Manufacturing

2

Shift Left Moving in Manufacturing

3

Shift Right Testing in Manufacturing

4

Shift Left Testing in Manufacturing

11

Multiple Choice

Paper: Improving PreHVS Sidd Yield Loss via Optimization of GIDL-Related Process Parameters in 3nm

Question: Which process parameter could affect GIDL and is newly discovered at this work?

1

FinCD

2

Gox Thickness

3

S/D Proximity

4

Poly Footing

ATS 2024:
Track 2

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