Computer Organization and Architecture

A bus scores over a multistage switching network in which one of the following aspects

• Reliability

• Speed

• Scalability

• Cost of Performing

The fetch and execution cycles are interleaved with the help of ________

• Modification in processor architecture

• Clock

• Special unit

• Control unit

To increase the speed of memory access in pipelining, we make use of _______

• Special memory locations

• Special purpose registers

• Cache

• Buffers

The situation wherein the data of operands are not available is called ______

• Data hazard

• Stock

• Deadlock

• Structural hazard

What does the hardwired control generator consist of?

• Decoder/encoder

• Condition codes

• Control step counter

• All of the mentioned

The type of control signal is generated based on ________

• contents of the step counter

• Contents of IR

• Contents of condition flags

• All of the mentioned

A sequence of control words corresponding to a control sequence is called _______

• Micro routine

• Micro function

• Micro procedure

• None of the mentioned

To read the control words sequentially _________ is used.

• PC

• IR

• UPC (MPC)

• None of the mentioned

Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is ________

• Horizontal organisation

• Vertical organisation

• Diagonal organisation

• None of the mentioned