UT- 2 (Quiz on verilog)

The input and output ports should be declared inside the ________

• Module

• Case

• wire

• None of the above

Which of the following loops are

supported by verilog?

• if-else loop

• for loop

• while loop

• All the above

The designers of Verilog wanted a language with syntax similar to the ________, which was already widely used in engineering software development

• Pointer

• python

• C Programming

• None of the above

VHDL uses an ___________declaration to

describe how a component or block should perform

• Architectural

• Behavioral

• Module

• None of the above

The "structural"style of programming in Verilog _________the designer to use sequential semantics to define the behavior of a hardware component or block

• does not allow

• allows

• allows with condition

• None of the above

One particular pitfall is the accidental production of ________ rather than D-type flip-flops as storage elements.

• Integrated circuit

• Latch (electronics)

• NAND gate

• Logic gate

Which level of abstraction level is available in Verilog but not in VHDL?

• Behavioral level

• Structural level

• Dataflow level

• Switch level

Which logic level is not supported by

verilog?

• U

• X

• Z

• None of the above

Variable and signal which will be updated first?

• variable

• signal

• can't say

• None of the above

Which of the following is true about parameters?

• The default size of a parameter in most synthesizers is the size of an integer, 32 bits

• Parameters enable Verilog code to be compatible with VHDL

• Parameters cannot accept a default value

• All of the above