Flip - Flops

An SR-latch is created using only two NOR gates with S and R inputs feeding one NOR gate each. If both S and R inputs are set to one, the outputs will be

• a. Q and Q' both 1

• b. No change in circuit output

• c. Q and Q' both 0

• d. Q and Q' complementary to each other

Consider the circuit shown below. Which of the following statements is true?

• a. The circuit would hold the previous state for S = 0, R = 0.

• b. The circuit would hold the previous state for S = 0, R = 1.

• c. The circuit would hold the previous state for S = 1, R = 1.

• d. The circuit would never be able to hold the previous state under any condition

You are having a D flip-flop, which you want to use as a J-K flip-flop. The input of the D flipflop in terms of external inputs J and K can be written as (Consider Qn is the output of the D flip-flop)

• a. D = JQn + KQn

• b. D = J’Qn + K’Qn

• c. D = JQ’n + K’Qn

• d. D = JQ’n + KQ’n

You are having a D flip-flop, which you want to use as a S-R flip-flop. The input of the D flipflop in terms of external inputs S and R can be written as (Consider Qn is the output of the D flip-flop)

• a. D = S + RQn

• b. D = S + R’Qn

• c. D = S’ + RQn

• d. D = S’ + R’Qn

Which of the following statements is NOT correct?

• a. Race around condition occurs in a JK latch when both the inputs are one.

• b. A flip flop is used to store one bit information.

• c. A transparent latch is D-type flip-flop with enable (level triggered) in place of a clock.

• d. Master-slave configuration is used in flip-flop to store two bits information.

The logic function depicting the behavior of the complementary output of T flip-flop is given by

• a. Q’ = T XOR Q

• b. Q’ = T XNOR Q

• c. Q’ = T OR Q

• d. Q’ = T NOR Q

The logic function depicting the behaviour of the complementary output of JK flip-flop is given

by

• a. Q’ = J’Q’ + KQ

• b. Q’ = JQ’ + K’ Q

• c. Q’ = J’K’

• d. Q’ = J’K’ + Q

A positive edge triggered D flip flop is connected as shown in the figure below. What would be the Q output in relation to the clock? Assume Q is initially 0.

• a. Timing Diagram A

• b. Timing Diagram B

• c. Timing Diagram C

• d. Timing Diagram D

Serial inputs are applied in the following manner to the J-K flip flop through AND gates as shown in the figure. What would be the resulting serial data that would be present at the output Q? There is one clock pulse for each bit time. Assume that Q is initially 0. Preset and Clear signals are always high. The input bits are applied from left to right.

• a. Q : 0 0 1 1 0 0 0

• b. Q : 1 0 1 1 0 0 0

• c. Q : 0 0 1 1 1 1 1

• d. Q : 0 0 0 1 0 0 0

Which of the following statements is/are true?

• A flip-flop is a level-sensitive storage element.

• A latch is a level-sensitive storage element.

• A latch is triggered both at the positive as well as the negative edges of a clock.

• A combinational circuit is triggered either at the positive edge or at the negative edge of a clock.