The gate region consists of ____________

• a) insulating layer

• b) conducting layer

• c) lower metal layer

• d) p type layer

In CMOS fabrication, nMOS and pMOS are integrated in same substrate.

• a) true

• b) false

Which model is used for scaling?

• a) constant electric scaling

• b) constant voltage scaling

• c) constant electric and voltage scaling

• d) constant current model

In enhancement mode, device is in _________ condition.

• a) conducting

• b) non conducting

• c) partially conducting

• d) insulating

MOS transistor structure is ____________

• a) symmetrical

• b) non symmetrical

• c) semi symmetrical

• d) pseudo symmetrical

In MOS transistors _______________ is used for their gate.

• a) metal

• b) silicon-di-oxide

• c) polysilicon

• d) gallium

Enhancement mode device acts as ____ switch, depletion mode acts as _____ switch.

• a) open, closed

• b) closed, open

• c) open, open

• d) close, close

The photoresist layer is exposed to ____________

• a) Visible light

• b) Ultraviolet light

• c) Infra red light

• d) LED

The ______ is used to reduce the resistivity of poly silicon.

• a) Photo resist

• b) Etching

• c) Doping impurities

• d) None of the mentioned

Consider a MOS structure with equilibrium Fermi potential of the doped silicon substrate is given as 0.3eV. Electron affinity of Si is 4.15eV and metal is 4.1eV. Find the built in potential of the MOS system.

• a) 0.6eV

• b) 0.8eV

• c) 0.9eV

• d)-0.9eV