DPSD IAT-III MCQ

Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

• input clock pulses are applied only to the first and last stages

• input clock pulses are applied only to the last stage

• input clock pulses are not used to activate any of the counter stages

• input clock pulses are applied simultaneously to each stage

One of the major drawbacks to the use of asynchronous counters is that:

• low-frequency applications are limited because of internal propagation delays

• high-frequency applications are limited because of internal propagation delays

• Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.

• Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.

Asynchronous circuits are useful in application where the input signal may

• Change at any time

• Never change

• both A and B

• Continuously change

The table that is not a part of the asynchronous analysis procedure is

• transition table

• state table

• flow table

• Excitation table

What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?

• The output word decreases by 1.

• The output word decreases by 2.

• The output word increases by 1.

• The output word increases by 2.

Which one is not the type of hazard

• Static-0 Hazard

• Static-1 Hazard

• Dynamic Hazard

• None of the above

In a logic circuit an Hazard is independent from

• Delay Existing

• Clock Pulses

• Latches

• Feedback

The dynamic hazard problem occurs in

• Combinational circuit alone

• Sequential circuit only

• Both (1) and (2)

• None of these

Which one is the suitable to detecting the hazard in circuit?

• Karnaugh map

• Boolean expression

• Logic gates

• None of these

Which circuit hazards must be eliminated?

• Sequential circuit

• Multiprocessor

• Combinational circuit

• Decoder