Mechatronics - Flip Flops - Chapter 7

Flip-flops are wired together to form sequential logic circuits.

• True

• False

Flips-flops are wired together to form combinational logic circuits.

• True

• False

On a flip-flop, the complementary output (Q') is always at the same logic state as the normal (Q) output.

• True

• False

The complementary output (Q') of a flip-flop is always at the opposite logic state from the normal (Q) output.

• True

• False

To set a flip-flop means to force the normal (Q) output to a 1 or HIGH.

• True

• False

To reset a flip-flop means to force the normal (Q) output to a 1 or HIGH.

• True

• False

The C input on the IEEE logic symbol means a control input which is the clock input to the J-K flip-flop.

• True

• False

The basic building block of combinational logic circuits is the ____.

• Flip-flop

• Flash memory cell

• Logic gate

• Timer

The basic building block of sequential logic circuits is the ______.

• Amplifier

• Flip-flop

• Rectifier

• Multiplexer

• Timer

During time period t₁, the R-S flip-flop is in the ____ mode of operation.

• Hold

• Reset

• Set