VERILOG DATA TYPES

Verilog HDL is a case-sensitive language. All keywords are in _________.

• lowercase

• uppercase

• either lower or uppercase

• bold letters

Whitespace is ignored by Verilog except when it separates _________.

• tokens

• streams

• comments

• ASCII

Which is illegal in writing comments in verilog?

• Embedding one-line comments in multiple-line comments

• Embedding multiple-line comments in multiple-line comments

• Embedding one-line comments after ;

• all of the given

Which is a unary operator?

• a = b && c;

• a = ~b;

• a = b & c;

• a = b ? c : d;

Numbers that are specified without a <base format> specification are __________ numbers by default.

• binary

• decimal

• octal

• hexadecimal

For a 32-bit Windows, the specified number: 8'd255 has how many bits?

• 32

• 16

• 8

• 4

For a 32-bit Windows, the specified number: 255 has how many bits?

• 32

• 16

• 8

• 4

Default value of a net is ___.

• 0

• 1

• x

• z

Default value of a reg data type is ___.

• 0

• 1

• x

• z

Which of the following vector part selection is considered ILLEGAL for the given example:

wire [7:0] bus;

reg [0:31] virtual_add;

• bus[5]

• bus[1:0]

• virtual_add[5:0]

• virtual_add[0]