ECE212_Sequenctial2

Dynamic latches

• are smaller than static ones

• have larger clock load

• have smaller clock load

• are larger than static ones

TSPC latches

• require differential clocks

• are smaller than C2MOS latches

• can have embedded logic

• are static latches

Pipelining

• increases throughput

• decreases throughput

• increases latency

• decreases latency

Clock load is minimal in

• TG static latch

• NMOS only latch

• pseudo static latch

• dynamic latch

A C2MOS register requires how many transistors?

• 4

• 6

• 8

• 12