2023-2024 Midterm HDL Part 1

A Syntax is a block of Verilog code that implements a certain functionality.

• TRUE

• FALSE

A module should be enclosed within module and endmodule.

• TRUE

• FALSE

You do not need to declare all variables, dataflow statements, functions within a module.

• TRUE

• FALSE

Ports are a set of signals that act as inputs and outputs to a particular module.

• TRUE

• FALSE

Ports are not the primary way of communication in the Verilog.

• TRUE

• FALSE

Assign statement are also called continuous assignments and are always active.

• TRUE

• FALSE

An initial block can be converted into hardware schematic and digital elements.

• TRUE

• FALSE

A Verilog case statement starts with begin keyword and ends with the end keyword.

• TRUE

• FALSE

Execution will exit the case block without doing anything if none of the items match the expression.

• TRUE

• FALSE

Sequence detector is the very common example of an FSM where the hardware design is expected to detect when a fixed pattern is seen in a stream of binary bits that are input to it.

• TRUE

• FALSE