LCD Reviewer

Latches are used to

• store single bit

• store 2 bits

• store 1 byte

• none of the above

SR latches use

• NAND gates

• NOR gates

• AND gates

• OR gates

When S=1 and R=0, what will happen

• Q=0 (reset)

• q'=1

• Q=1 (set)

• Q=no change (latch)

• invalid state q' = Q

When S=0 and R=0, what will happen

• Q=0 (reset)

• q'=1

• Q=1 (set)

• Q=no change (latch)

• invalid state q' = Q

When S=0 and R=1, what will happen

• Q=0 (reset)

• q'=1

• Q=1 (set)

• Q=no change (latch)

• invalid state q' = Q

When s'=1 and r'=1, what will happen

• Q=0 (reset)

• q'=1

• Q=1 (set)

• Q=no change (latch)

• invalid state q' = Q

When s'=0 and r'=1, what will happen

• Q=0 (reset)

• q'=1

• Q=1 (set)

• Q=no change (latch)

• invalid state q' = Q

When s'=1 and r'=0, what will happen

• Q=0 (reset)

• q'=1

• Q=1 (set)

• Q=no change (latch)

• invalid state q' = Q

When s'=0 and r'=0, what will happen

• Q=0 (reset)

• q'=1

• Q=1 (set)

• Q=no change (latch)

• invalid state q' = Q

If we create a D latch from either a SR or a s'r' latch, when D=1 and E=1 what will happen

• D=0 (reset)

• d'=1

• D=1 (set)

• no change in D (latch)

• invalid state d' = D