Rechnerarchitektur 2022/23

Which of these statements regarding pipelining is true?

• The instruction latency is reduced (thus improved)

• Pipelining works especially well on CISC architectures

• Multiple instructions are issued at the same time

• A 5-stage pipeline needs 4 additional buffer registers

The "Forwarding"-approach aims to mitigate...

• Data Hazards

• Control Flow Hazards

• Backward Hazards

• Structural Hazards

Which of these is a dynamic branch prediction strategy?

• Branch not taken

• Delayed branch

• Stall

• Branch History Table

Which of these is NOT a data hazard type?

• WAW

• WAR

• RAR

• RAW

Which of these statements is true?

• A scoreboard based architecture requires a multi-issue frontend.

• The Common Data Bus enables cache coherency

• A ROB makes it possible to rollback speculatively executed instructions

• Register renaming is a paid customisation feature by Intel so you can give your registers cute nicknames

Cache Configuration: 256 Byte size, 32 Byte Block Size, 4 Sets. What's the organisation form?

• Fully associative

• Direct Mapping

• 4-way associative

• 2-way associative

Which statement is correct?

• Caches aim to reduce temporal locality.

• Removing data from a cache is called a "cache miss".

• CPU caches are usually located inside the RAM.

• L2 Caches are usually slower than L1 Caches.

MESI is...

• a cache coherency protocol

• a combination of pipelining and superscalarity

• a Multicore Embedded Software Interface

• a dating platform

Performance gain = sqrt(Complexity). As said by...

• Pollack

• Amdahl

• Stallings

• Santa

Roofline model: The flat part of the roof is caused by...

• the max. memory bandwidth

• the max. computational performance

• the total memory size

• the problem size