Which of these statements regarding pipelining is true?

Rechnerarchitektur 2022/23

Quiz
•
Computers
•
University
•
Medium

Tobias Baumeister
Used 1+ times
FREE Resource
13 questions
Show all answers
1.
MULTIPLE CHOICE QUESTION
45 sec • 1 pt
The instruction latency is reduced (thus improved)
Pipelining works especially well on CISC architectures
Multiple instructions are issued at the same time
A 5-stage pipeline needs 4 additional buffer registers
2.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
The "Forwarding"-approach aims to mitigate...
Data Hazards
Control Flow Hazards
Backward Hazards
Structural Hazards
3.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Which of these is a dynamic branch prediction strategy?
Branch not taken
Delayed branch
Stall
Branch History Table
4.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Which of these is NOT a data hazard type?
WAW
WAR
RAR
RAW
5.
MULTIPLE CHOICE QUESTION
45 sec • 1 pt
Which of these statements is true?
A scoreboard based architecture requires a multi-issue frontend.
The Common Data Bus enables cache coherency
A ROB makes it possible to rollback speculatively executed instructions
Register renaming is a paid customisation feature by Intel so you can give your registers cute nicknames
6.
MULTIPLE CHOICE QUESTION
45 sec • 1 pt
Cache Configuration: 256 Byte size, 32 Byte Block Size, 4 Sets. What's the organisation form?
Fully associative
Direct Mapping
4-way associative
2-way associative
7.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Which statement is correct?
Caches aim to reduce temporal locality.
Removing data from a cache is called a "cache miss".
CPU caches are usually located inside the RAM.
L2 Caches are usually slower than L1 Caches.
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