Computer Architecture

Computer Architecture

9th - 12th Grade

22 Qs

quiz-placeholder

Similar activities

Text and Image representation

Text and Image representation

11th Grade

22 Qs

IT (data, viruses and more)

IT (data, viruses and more)

8th Grade - Professional Development

20 Qs

Practice Quiz for Term 1

Practice Quiz for Term 1

10th Grade

20 Qs

ICT WEBINAR QUIZ

ICT WEBINAR QUIZ

KG - Professional Development

20 Qs

PH Infromatika kls IX Bab 4, 5, 6

PH Infromatika kls IX Bab 4, 5, 6

9th Grade

20 Qs

Computer Fundamentals

Computer Fundamentals

10th Grade

20 Qs

End of unit assessment - Networks

End of unit assessment - Networks

9th Grade

18 Qs

xXQuiz Sobre iOSXx

xXQuiz Sobre iOSXx

10th - 12th Grade

18 Qs

Computer Architecture

Computer Architecture

Assessment

Quiz

Computers

9th - 12th Grade

Practice Problem

Hard

Created by

Ryan Coughlin

Used 41+ times

FREE Resource

AI

Enhance your content in a minute

Add similar questions
Adjust reading levels
Convert to real-world scenario
Translate activity
More...

22 questions

Show all answers

1.

MULTIPLE SELECT QUESTION

45 sec • 1 pt

What are the 4 fundamental components of the von Neumann machine?

input/output

ALU

Control Unit

Memory Unit

Buses

2.

FILL IN THE BLANK QUESTION

1 min • 1 pt

Computers are able to be programmed because of the s_____ p______ c______

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In a von Neumann computer, where are the program instructions stored?

memory

storage

buses

buffers

4.

MULTIPLE SELECT QUESTION

45 sec • 1 pt

Which is not a register?

PC

MAR

MDR

CIR

ALU

5.

REORDER QUESTION

1 min • 1 pt

What are the steps of the fetch decode execute cycle

instruction from memory address (sent from MAR) is sent along data bus to MDR

Address in MAR is sent along address bus, "read" signal is sent along control bus

PC increments by 1

Value in PC is sent to MAR

instruction in MDR is sent to CIR, is then decoded and executed

6.

REORDER QUESTION

1 min • 1 pt

What are the steps of reading from memory to the CPU

Value in MAR is sent along address bus, a "read" signal is sent along the control bus

Address to read is put into MAR

Data is now in MDR

Data pointed to by address (in MAR) is sent along data bus to MDR

7.

MULTIPLE SELECT QUESTION

45 sec • 1 pt

Which bus is always bidirectional?

data

control

system

address

Access all questions and much more by creating a free account

Create resources

Host any resource

Get auto-graded reports

Google

Continue with Google

Email

Continue with Email

Classlink

Continue with Classlink

Clever

Continue with Clever

or continue with

Microsoft

Microsoft

Apple

Apple

Others

Others

Already have an account?