Surprize quiz III

THUMB instruction size is

• 32 bit

• 64 bit

• 16 bit

• 8 bit

Which following register is used as stack pointer in ARM7 processor?

• R12

• R13

• R14

• R15

In ARM7 processor, CPSR contains________number of condition flags.

• 3

• 4

• 5

• 6

CPSR stands for

(a)  

Select correct syntax of the ARM instruction

• ADD r16, r1, r3

• ADD A, r1

• ADD r0

• ADD r0, r1, r2

Which of the following register in ARM7 is used to point to the location of currently executing instruction in a program?

• R12

• R13

• R14

• R15

See the figure and find out the register content after execution of following instruction (INITIALLY R0=0x010):

LDMIB R0!, {R2, R3, R1}

• r1=10

  r2=30

  r3=40

  r0=0x010

• r1=10

  r2=20

  r3=30

  r0=0x01C

• r1=20

  r2=20

  r3=30

  r0=0x010

• r1=20

  r2=30

  r3=40

  r0=0x01C

Which of the following instruction corresponds to loading signed half-word in ARM?

• LDSH

• LDRH

• LDSHW

• LDRSH

Which of the following operation is performed by the following instruction:

LDR R0, [R1], #8

• R0 loaded with contents of memory location specified by R1

• R0 loaded with contents of memory location specified by R1+8

• R0 loaded with contents of memory location specified by R1-8

• R1 loaded with contents of memory location specified by R0+8

The instruction "ADC R0, R1, R2, LSL #2" will affect CPSR.

• True

• False