UNIT 2

How many units does VHDL design consists?

• One

• Two

• Three

• Four

What is the use of VHDL language?

• Provides machine readable documentation

• Provides human readable documentation

• Both a and b

• None of the above

Which one of the following is a VHDL logical (Boolean) operator?

• Equality

• Inequality

• Less than

• Not

Which one of the following is a VHDL relational operator?

• Not

• Equality

• NAND

• AND

Which one of the following, one manages the large design?

• VHDL

• Verilog

• Both a and b

• None of the above

The difference output in a full-subtractor is the same as the

• • difference output of a half-subtractor

• sum output of a half-adder

• • sum output of a full-adder

• • carry output of a full-adder

The logic gate used in parity checkers is

• • NAND gate

• • NOR gate

• • X-OR gate

• • X-NOR gate

A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called

• an encoder

• • a decoder

• • a code convener

• • a decimal converter

A logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output is called

• • a multiplexer

• • a demultiplexer

• • a transmitter

• • a receiver

A demultiplexer with 4-bit select input has

• • one data input and four data output lines

• • one data input and eight data output lines

• • one data input and ten data output lines

• • one data input and sixteen data output lines