UNIT 2

UNIT 2

University

10 Qs

quiz-placeholder

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UNIT 2

UNIT 2

Assessment

Quiz

Other

University

Practice Problem

Hard

Created by

Sivaprakash P

Used 2+ times

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10 questions

Show all answers

1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

How many units does VHDL design consists?

One

Two

Three

Four

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the use of VHDL language?

Provides machine readable documentation

Provides human readable documentation

Both a and b

None of the above

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which one of the following is a VHDL logical (Boolean) operator?

Equality

Inequality

Less than

Not

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which one of the following is a VHDL relational operator?

Not

Equality

NAND

AND

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which one of the following, one manages the large design?

VHDL

Verilog

Both a and b

None of the above

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

The difference output in a full-subtractor is the same as the

  • difference output of a half-subtractor

sum output of a half-adder

  • sum output of a full-adder

  • carry output of a full-adder

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

The logic gate used in parity checkers is

  • NAND gate

  • NOR gate

  • X-OR gate

  • X-NOR gate

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