OCR Computer Science Pipelining

OCR Computer Science Pipelining

12th Grade

9 Qs

quiz-placeholder

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OCR Computer Science Pipelining

OCR Computer Science Pipelining

Assessment

Quiz

Computers

12th Grade

Medium

Created by

Margaret Sifuna

Used 15+ times

FREE Resource

9 questions

Show all answers

1.

MULTIPLE CHOICE QUESTION

1 min • 5 pts

What is pipelining in computer science?

A technique that allows multiple instructions to be executed simultaneously by dividing them into larger stages and processing them in parallel.

A technique that allows multiple instructions to be executed randomly by processing them in any order.

A technique that allows multiple instructions to be executed sequentially by processing them one after another.

A technique that allows multiple instructions to be executed simultaneously by dividing them into smaller stages and processing them in parallel.

2.

MULTIPLE CHOICE QUESTION

1 min • 5 pts

What are the advantages of pipelining?

Improved performance, reduced execution time, increased throughput, better resource utilisation

Increased complexity, higher cost, more resource consumption, reduced efficiency

No impact on performance, execution time, throughput, or resource utilisation

Decreased performance, longer execution time, decreased throughput, worse resource utilisation

3.

MULTIPLE CHOICE QUESTION

1 min • 5 pts

What are the stages involved in the pipelining process?

instruction fetch, instruction decode, execution, memory access

instruction fetch, instruction decode, execution, memory access, write back

instruction fetch, instruction decode, execution, memory access, and write back

instruction fetch, instruction decode, execution, memory access, write back

4.

MULTIPLE CHOICE QUESTION

1 min • 5 pts

Explain the concept of data hazards in pipelining.

Data hazards occur when there is a mismatch in the instruction set architecture.

Data hazards occur when there is a delay in executing instructions.

Data hazards occur when there is a dependency between instructions that causes a conflict in accessing or modifying data.

Data hazards occur when there is a hardware malfunction in the pipeline.

5.

MULTIPLE CHOICE QUESTION

1 min • 5 pts

What is instruction-level parallelism?

Ability of a processor to execute multiple instructions sequentially

Ability of a processor to execute multiple instructions simultaneously

Ability of a processor to execute one instruction at a time

Ability of a processor to execute instructions in a random order

6.

MULTIPLE CHOICE QUESTION

1 min • 5 pts

How does pipelining improve the performance of a processor?

By allowing multiple instructions to be executed simultaneously and overlapping the execution of different stages of instructions.

By limiting the number of instructions that can be executed at a time.

By increasing the number of clock cycles required for each instruction.

By reducing the clock speed of the processor.

7.

MULTIPLE CHOICE QUESTION

1 min • 5 pts

What is the difference between pipelining and parallel processing?

Pipelining is the overlap of instruction execution, while parallel processing is the simultaneous execution of multiple tasks.

Pipelining is the same as parallel processing.

Pipelining is the execution of multiple tasks simultaneously.

Parallel processing is the overlap of instruction execution.

8.

MULTIPLE CHOICE QUESTION

1 min • 5 pts

What are the potential challenges or limitations of pipelining?

Data dependencies, branch instructions, and resource contention.

Data hazards, instruction hazards, and control hazards.

Parallelism, cache size, and instruction level parallelism.

Memory access, clock speed, and instruction set.

9.

MULTIPLE CHOICE QUESTION

1 min • 5 pts

How can pipelining be implemented in a CPU architecture?

By executing instructions sequentially without any parallelism.

By increasing the clock speed of the CPU.

By reducing the number of stages in the instruction execution process.

By breaking down the execution of instructions into multiple stages and allowing each stage to work on a different instruction simultaneously.