20EC204 Digital System Design (2023--24) Surprise Quiz - II

In Verilog, the data types can accept only ________ number of  states/ logic.

• 4

• 3

• 2

• 6

In VLSI Design flow, the Circuit Design is followed by _________ level.

• Architectural Design

• Functional Design

• Physical Design

• Logic Design

In _________ style of modeling, logic blocks are realized by writing their Boolean expression

• Gate Level

• Data Flow

• Behavioral

• Structural

Verilog, standardized as ___________, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

• IEEE 1764

• IEEE 1364

• IEEE 1800

• IEEE 1900

In gate level modeling, “ bufif0” belongs to which type of built-in  primitive gates?

• multiple-input, gates

• multiple-output gates

• tri-state gates

• pull gates

____________ is the purpose of the “module” keyword in Verilog.

• To define a new data type

• To define a new function

• To define a new hardware module

• To define a new system task

The time taken for the output of a gate to change from some value to 1 is called a ________.

• turn-off delay

• fall delay

• rise delay

• positive delay

The maximum number of inputs to a combinational user defined primitive (UDP) is _______.*

• 4

• 6

• 8

• 10

he below given code is the Verilog code for Half adder using __________ modelling.

modulehalf_adder(a,b,sum,cout);

inputa,b;

outputsum,cout; // sum and carry

xorx1(sum,a,b);

anda1(cout,a,b);

endmodule

• Gate Level

• Data Level

• Behavioral

• Structural

__________abstraction level is based on synchronous logic and contains three primary pieces namely, registers which hold state information, combinatorial logic which defines the nest state inputs, and clocks that control when the state changes.

• Register Transfer Level(RTL)

• Gate Level

• HDL

• Behavorial Level