DE: Unit 3 Review

DE: Unit 3 Review

12th Grade

18 Qs

quiz-placeholder

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DE: Unit 3 Review

DE: Unit 3 Review

Assessment

Quiz

Other

12th Grade

Hard

Used 3+ times

FREE Resource

18 questions

Show all answers

1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the limitation of the 74LS93 counter?

It can only be used to implement up counts

It can be used to implement both up and down counts

It can only be used to implement down counts

The flip-flops are pre-settable

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the primary difference between a D flip-flop and a D latch?

The flip-flop has transparent inputs while the latch does not

The flip-flop has asynchronous inputs while the latch does not

The clock input is edge sensitive for the flip-flop and level sensitive for the latch

The clock input is level sensitive for the flip-flop and edge sensitive for the latch

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the purpose of asynchronous inputs (Preset & Clear) in a flip-flop?

To override the clock/data inputs and force the outputs to a predefined state

To synchronize the clock and data inputs for accurate timing

To provide additional clock cycles for data processing

To enable transparent latching of data inputs

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the function of the Enable (EN) input in a transparent D-latch?

To provide additional clock cycles for data processing

To override the clock/data inputs and force the outputs to a predefined state

To control when the latch is transparent or latched

To synchronize the clock and data inputs for accurate timing

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which type of flip-flop has a positive edge-triggered clock input?

Quad latch

D flip-flop

J/K flip-flop

D latch

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the timing interval before the active transition of the clock signal during which the data input must be maintained called?

Hold Time (tH)

Preset Time (tP)

Clear Time (tC)

Setup Time (tS)

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which component is used to force the output of a flip-flop to a predefined state?

Data input

Clock input

Enable input

Asynchronous inputs (Preset & Clear)

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