ACA Quiz Unit 2

Cache memory is in ____ range

• KB

• GB

• TB

Set is made up of blocks

• False

• True

Block address is chosen by the address of data given by (Block address) MOD (Number of sets in cache)

• True

• False

A fully associative cache has a single

• Set

• Block

Write Through Cache updates

• The Cache

• The Memory

• All of the above

Average memory access time is

• Miss Time +Hit time *Miss Penalty

• Hit time + Miss rate x Miss Penalty

• Hit time x Miss rate +Penalty

SRAM utilizes ___ transistors per bit

• 4

• 6

• 2

• 1

What is CAS

• Computer Access Society

• Computer access station

• Column addressable strobe

• Column access strobe

Number of steps in a refresh is the square root of the DRAM capacity

• True

• False

3 Cs model has the following categories

• Computer, Cache and Capacity

• Complementary, Cache and Conflict

• Compulsory, Capacity and Conflict