VLSI

In positive logic conversion for inverters, the condition for output voltage =VDD is:

• Input voltage must be Zero

• Input voltage between 0 to Vth

• Input voltage between Vth to VDD

• Input voltage must be VDD

In Y-chart representation of VLSI design flow, which one of these parameters does not fall in the structural domain?

• a) Processor

• b) Leaf cell

• c) Register ALU

• d) Cell placement

The junction parasitic capacitance is produced due to ____

• a) Source diffusion regions

• b) Gate diffusion regions

• c) Drain diffusion regions

• d) All of the above

If at zero gate bias voltage, no conducting channel region is present, than the operating mode of MOS transistor is called as...

• a) Mixed mode

• b) Cut-off mode

• c) Enhancement mode

• d) Depletion mode

If the acceptor concentration MOS transistor is increased, then the threshold voltage will...

• a) Increase

• b) Decrease

• c) Independent of the acceptor quantity

• d) Null effect

Thermal noise in MOSFET is proportion to:

• Transconductance

• Resistance

• Gate voltage

• None of the mentioned

According to the ITRS roadmap, what was the feature size for metal oxide semiconductor in 2010s?

• a) 65nm

• b) 45nm

• c) 22nm

• d) 10nm

To operate the resistive load inverter in the saturation region, the range of input voltage (Vin) is.

• Vin > VT0

• Vin < VT0

• VT0 ≤ Vin ≤ Vout + VT0

• VT0 ≥ Vin ≥ Vout + VT0

For an n-channel MOSFET, if the conduction parameter (Kn) is 0.249 mA/V^2, gate to source voltage VGS = 1.5V and VTH=0.75V. The current will be?

• a) 0.160 mA

• b) 0.150 mA

• c) 0.140 mA

• d) 0.130 mA

If 푉SB=0, 푁A=4×10^18 cm^-3 and 푁D=2×10^20 cm^-3, then what the fermi potential for p-type substrate?

• a) -0.55V

• b) 0.51V

• c) -0.51V

• d) 0.55V