Memory and Cache Quiz

Structural Hazard:

• An instruction in the pipeline needs a resource being used by another instruction in the pipeline

• An instruction depends on a data value produced by an earlier instruction

• Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

Cache MISS:

• No Write Allocate, Write Allocate

• Write Through, Write Back

What is a Bandwidth?

• a is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI

• is time for a single access - Main memory latency is usually >> than processor cycle time

• is amount of data that can be in flight at the same time (Little's Law)

What is a Latency?

• is time for a single access - Main memory latency is usually >> than processor cycle time

• is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle

• is amount of data that can be in flight at the same time (Little's Law)

What is Computer Architecture?

• is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies

• is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users

• the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them

The formula of "Iron Law" of Processor Performance:

• time/program = instruction/program (cycles/instruction) time/cycle

• time/program = instruction/program * (cycles/instruction) + time/cycle

• time/program = instruction/program + (cycles/instruction) * time/cycle

What is a Bandwidth-Delay Product?

• is amount of data that can be in flight at the same time (Little's Law)

• is time for a single access - Main memory latency is usually >> than processor cycle time

• is the number of accesses per unit time - If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI

Conflict -

• first-reference to a block, occur even with infinite cache

• misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

• cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?

• subroutine call

• n loop iterations

• vector access

Algorithm for Cache HIT:

• Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache

• Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache

• Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache