UNIT 3-STA

______________ is focused primarily in designing of electronic circuits.

• Time Delay

• Phase Delay

• Propagation Delay

• Angular Delay

Propagation delay increase with _____________.

• Conductance

• Inductance

• Operating Temperature

• Operating Voltage

Example assumes that tPLH and tPHL equal 20 ns for both AND and NOR gate. Find out the Total propogation delay when A=0, Ci=1

• 20ns

• 40ns

• 80ns

• 10ns

Minimum Time Period (Tminimum) or Maximum clock operating frequency (fmaximum)

• Tsetup_time + Tclock_Q + delay <= Tminimum

• Tsetup_time + Tclock_Q <= Tminimum

• Tsetup_time + delay <= Tminimum

• Tsetup_time + Tclock_Q + delay <= Tminimum

Given the following flip-flop circuit with a delay dly between input and output. And the clock CLK is applied to the flip flop.he expression will be for minimum clock period will be as below,

Tminimum >= Tsetup_time + Tclock_Q + dly.

what is the Tminimum for FF3.

Tclock_Q1=5 Tclock_Q2=6 Tclock_Q3=8

Tsetup_time1=3 Tsetup_time2=4 Tsetup_time3=2

Thold_time1=2 Thold_time2=1 Thold_time3=1

• 10ns

• 5ns

• 20ns

• 40ns

The time required for an input data to settle _____ the triggering edge of clock is known as ‘Setup Time’.

• Before
  

• During
  

• After
  

• All of the above

Before the commencement of design, the clocking strategy determine/s __________

• Number of clock signals necessary for routing throughout the chip
  

• Number of transistors used per storage requirement
  

• Power dissipated by chip & the size of chip
  

• All of the above

For an edge triggered register in master slave configuration, propagation delay

of inverter and transmission gate is 2ns and 5 ns respectively. Find its clock-to-q delay

• 11 ns

• 7 ns

• 0 ns

• 2 ns

he Lower Noise Margin is given by:

• VOL – VIL
  

• VIL – VOL

• VIL ~ VOL(Difference between VIL and VOL, depends on which one is greater

• All of the Mentioned

Identify the unateness and timing arc

• Positive

• negative

• non unate

• negative timing arc