G8 Fetch Decode Execute Cycle

Carries data around the CPU

• Buses

• Clock

• Control Unit

• Arithmetic Logic Unit

• Registers

It regulates the cycle per second

• Buses

• Clock

• Control Unit

• Arithmetic Logic Unit

• Registers

These are fast action memory locations in the CPU

• Buses

• Clock

• Control Unit

• Arithmetic Logic Unit

• Registers

It manages and instructs other components in the CPU

• Buses

• Clock

• Control Unit

• Arithmetic Logic Unit

• Registers

It carries out mathematical calculation

• Buses

• Clock

• Control Unit

• Arithmetic Logic Unit

• Registers

Select all types of the CPU registers

• Memory Address Register (MAR)

• Memory Data Register (MDR)

• Current Instruction Register (CIR)

• Program Counter (PC)

• Random Access Memory (RAM)

It is the main memory of the computer

• Memory Address Register (MAR)

• Memory Data Register (MDR)

• Current Instruction Register (CIR)

• Program Counter (PC)

• Random Access Memory (RAM)

In the FDE Cycle

Instructions are loaded into memory (RAM) before the processor starts running the program.

• Fetch

• Decode

• Execute

• Store

In the FDE Cycle

The binary representation of an instruction needs to be decoded before it can be run. This is the process the control unit uses to work out what the other components need to do.

• Fetch

• Decode

• Execute

• Store

In the FDE Cycle

Once the instruction is understood, the instruction will be executed. The control unit will tell the other components what they need to do in order for the instruction to work.

• Fetch

• Decode

• Execute

• Store