Flip-Flop Characteristics Quiz

Which of the following is true for a D flip-flop?

• It has two inputs: J and K

• It has two inputs: S and R

• It has one input: D

• It has three inputs: D, S, and R

In a JK flip-flop, if both J and K inputs are high, the output will:

• Remain the same

• Reset

• Set

• Toggle

Which of the following is NOT a characteristic of a T flip-flop?

• It has a toggle mode

• It can be constructed from a JK flip-flop

• It has two stable states

• It requires two inputs: T and Clock

The primary difference between a latch and a flip-flop is:

• Latches are edge-triggered, while flip-flops are level-triggered

• Latches are level-triggered, while flip-flops are edge-triggered

• Latches have a clock input, while flip-flops do not

• There is no difference; both are the same

Which of the following is a type of flip-flop?

• JK flip-flop

• SR flip-flop

• D flip-flop

• All of the above

In a D flip-flop, if the D input is HIGH and the clock pulse is applied, what will be the output (Q)?

• HIGH

• LOW

• No change

• Toggle

What is the characteristic equation of a JK flip-flop?

• Q(next) = JQ' + K'Q

• Q(next) = JQ + K'Q'

• Q(next) = JQ + KQ'

• Q(next) = J'Q + KQ'

What is the output of an SR flip-flop when both the Set (S) and Reset (R) inputs are HIGH?

• Q = 0, Q' = 1

• Q = 1, Q' = 0

• Q = 0, Q' = 0

• Undefined

In an SR flip-flop, if the Set (S) input is HIGH and the Reset (R) input is LOW, what will be the output (Q)?

• Q = 0, Q' = 1

• Q = 1, Q' = 0

• Q = 1, Q' = 1

• Q = 0, Q' = 0

Edge triggering occurs when a flip-flop changes its state:

• When the clock signal is HIGH

• When the clock signal is LOW

• At the transition of the clock signal from LOW to HIGH or HIGH to LOW

• When the clock signal is stable