
EN QUIZ 2

Quiz
•
Engineering
•
University
•
Easy
Jayanthy Soundrarajan
Used 1+ times
FREE Resource
10 questions
Show all answers
1.
MULTIPLE CHOICE QUESTION
2 mins • 1 pt
In SPI protocol,-------signal is generated by Master to select individual slave/peripheral devices
Slave Select(SS)
Master In Slave Out (MISO)
Serial Clock(SCK)
Master Out Slave In (MOSI)
2.
MULTIPLE CHOICE QUESTION
2 mins • 1 pt
In SPI protocol, if the phase of the clock is zero data is latched at the ------- of the clock with clock polarity = 0
High Level
Low level
Rising edge
Falling edge
3.
MULTIPLE CHOICE QUESTION
2 mins • 1 pt
------ version of PCI bus Introduces Error Correction Codes mechanism to improve robustness and data integrity
PCI-X 1.0
PCI Express
PCI 2.1
PCI-X 2.0
4.
MULTIPLE CHOICE QUESTION
2 mins • 1 pt
IrDA uses a bit-encoding scheme known as---- to distinguish between a logic 0 and a logic 1 during transmission
RZ
NRZ
Manchester
NRZI
5.
MULTIPLE CHOICE QUESTION
2 mins • 1 pt
The basic purpose of IrDA is
to provide device-to-device communication over short distances
to provide device-to-device communication over long distances
to provide point to multipoint communication over short distances
to provide point to multipoint communication over long distances
6.
MULTIPLE CHOICE QUESTION
2 mins • 1 pt
The ---------------specification details the hardware layer, including requirements for modulating the outputs of UARTs prior to transmission in IrDA protocol
IrPHY
IrLAP
IrCOMM
IrOBEX
7.
MULTIPLE CHOICE QUESTION
2 mins • 1 pt
In I2C,START condition is indicated when the master-chip activates----
First the clock line (SCL) low, and next the data line (SDA) low
First the data line (SDA) low, and next the clock line (SCL) low
First the clock line (SCL) high, and next the data line (SDA) high
First the data line (SDA) high, and next the clock line (SCL) high
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