Gate-Level Modeling in Verilog Quiz

Which Verilog keyword is used to instantiate basic gates in gate-level modeling?

• module

• assign

• wire

• and

Which of the following represents a valid Verilog gate-level modeling instantiation for an AND gate?

• and A1 (output, input1, input2);

• and (output, input1, input2);

• and_gate (input1, input2, output);

• and_gate A1;

In gate-level modeling, what is the significance of the first argument in the gate instantiation?

• It represents the input to the gate.

• It represents the output of the gate.

• It represents the instance name of the gate.

• It represents the gate type.

Which basic logic gate is represented by the Verilog keyword xor?

• AND

• OR

• XOR

• XNOR

In gate-level modeling, how would you instantiate a 3-input OR gate?

• or O1 (out, in1, in2, in3);

• or O1 (out, in1, in2);

• or (in1, in2, in3, out);

• or_gate O1 (out, in1, in2, in3);

Which of the following gates is not available in Verilog's gate-level modeling?

• and

• nor

• xor

• xand

What is the purpose of the not gate in Verilog?

• It outputs 1 when both inputs are 1.

• It inverts the input signal.

• It outputs 1 when either input is 1.

• It passes the input unchanged.

In gate-level modeling, which Verilog primitive performs a logical NOR operation?

• nor

• xor

• xnor

• nand

Which of the following gates is an example of a "primitive" gate in Verilog?

• and, or, not

• nand, nor, xor

• xor, xnor, buf

• All of the above

What is the output of an AND gate in Verilog when one input is 0 and the other is 1?

• 0

• 1

• X

• Z