IHDL_Semi-Final Quiz

What is behavioral modeling in Verilog?

• Describes circuit functionality using gates.

• Describes circuit behavior using high-level constructs.

• Describes circuit connections using structural code.

• Describes physical layout of a circuit.

Which Verilog keyword is used to start a behavioral modeling block?

• module

• initial

• always

• Both b and c

What is the purpose of the always block in behavioral modeling?

• To define hardware gates explicitly.

• To describe how outputs change in response to inputs.

• To connect components structurally.

• To define physical pin locations.

In behavioral modeling, what is the sensitivity list in an always block?

• A list of variables declared as outputs.

• A list of signals that trigger the block to execute.

• A list of gates used in the design.

• A list of test cases for the module.

Which of the following is a valid sensitivity list for an always block?

• always @ (posedge clk)

• always @ (a or b)

• always @ (*)

• All of the above

What does always @ (*) indicate in behavioral modeling?

• The block executes only once.

• The block executes whenever any signal inside the block changes.

• The block executes periodically.

• The block executes during reset only.

Which of the following is NOT used in behavioral modeling?

• if-else statements

• case statements

• Gate-level primitives like and or or

• Loops like for or while

What is the difference between initial and always blocks?

• initial runs continuously, always runs once.

• initial runs once, always runs continuously.

• Both run continuously.

• Both run once at simulation start.

What is the primary use of initial blocks in behavioral modeling?

• To model combinational logic.

• To describe sequential logic.

• To provide stimulus or initialization in testbenches.

• To declare variables.

What type of logic is typically modeled using always @ (*)?

• Sequential logic

• Combinational logic

• Structural logic

• Physical logic