Surprise Quiz 2 - Digital System Design

Surprise Quiz 2 - Digital System Design

University

11 Qs

quiz-placeholder

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Surprise Quiz 2 - Digital System Design

Surprise Quiz 2 - Digital System Design

Assessment

Quiz

Engineering

University

Easy

Created by

Priyadharshini ECE

Used 5+ times

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11 questions

Show all answers

1.

OPEN ENDED QUESTION

20 sec • Ungraded

Enter Roll Number in full

Evaluate responses using AI:

OFF

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which model uses transistors as their basic components

Switch level

Gate Level

Circuit Level

Layout Level

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

State true or false for the statement 'Verilog is case sensitive'

True

False

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is Verilog?

A programming language for hardware description

A high-level programming language for software development

A data visualization tool

An operating system

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which one of the following represents a hardware component in Verilog

Module

Function

Loop

Variable

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the purpose of 'assign' statement in Verilog

To initialize variables

To specify input/output ports of a module

To implement continuous assignments for combinational logic

To define a new module

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In RTL Design, What is a 'register'

A clock signal generator

A storage element for data

An arithmetic logic unit (ALU)

A type of programming language

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