Surprise Quiz 2 - Digital System Design

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Which model uses transistors as their basic components

• Switch level

• Gate Level

• Circuit Level

• Layout Level

State true or false for the statement 'Verilog is case sensitive'

• True

• False

What is Verilog?

• A programming language for hardware description

• A high-level programming language for software development

• A data visualization tool

• An operating system

Which one of the following represents a hardware component in Verilog

• Module

• Function

• Loop

• Variable

What is the purpose of 'assign' statement in Verilog

• To initialize variables

• To specify input/output ports of a module

• To implement continuous assignments for combinational logic

• To define a new module

In RTL Design, What is a 'register'

• A clock signal generator

• A storage element for data

• An arithmetic logic unit (ALU)

• A type of programming language

What is the default value of the reg data type

• 0

• 1

• Z

• X

What is the purpose of the 'posedge' keyword in Verilog?

• To specify a positive edge-triggered flip flop

• To specify a negative edge-triggered flip flop

• To specify a synchronous reset

• To specify an asynchronous reset

How are multi-bit signals represented in Verilog

• As an array of bits

• As separate single-bit signals

• As a string of characters

• As a floating-point number