Physical Design Assignment Quiz

Buffers only allowed placement blockage

• Hard blockage

• Soft blockage

• Partial blockage

• None of the above

Find the maximum frequency of the block if the critical timing path has a positive slack value of 5ns for the time period of 25ns.

• 40MHz

• 33.3MHz

• 50MHz

• 1GHz

DRV refers to

• max cap, max tran, fanout;

• Antenna, max cap, max tran;

• Skew, Antenna, max tran

• Max cap, max tran, skew.

DRC related information present in

• .lib file

• .tf file

• Netlist

• DEF file

Which is not .lib contents

• Logical equation

• Timing information

• Power

• Pin dimension

Latch up violation will be eliminated by

• filler cells

• decap cells

• tap cells

• tie cells

Dynamic power can be controlled by

• Increasing the load capacitance

• Increasing the voltage

• Decreasing the doping concentrations

• Reducing the transition time

Floorplan steps order

• Die size fixing -> Port placement -> macro placement -> physical cell placement -> power planning

• Diesize fixing -> macro placement -> port placement-> physical cell placement -> power planning

• Power planning -> Die size fixing -> Port placement -> macro placement -> physical cell placement

• Die size fixing -> Port placement -> physical cell placement -> macro placement -> power planning.

Find skew on below timing path

• Insufficient data

• 5.2ns

• 0.7ns

• 4.5ns

Find max latency on below timing path

• Insufficient data

• 5.2ns

• 0.7ns

• 4.5ns