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Digital Logic Design Quiz

Authored by Maga Med

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University

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Digital Logic Design Quiz
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20 questions

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1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What are the two stable states in a latch or flip flop?

High and Low

True and False

Logic 1 and Logic 0

On and Off

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the purpose of the excitation table in the design of flip flops and counters?

To show the result of the next state based on the control input

To show the minimum inputs required for the particular next state

To derive the truth table

To show the output as the inputs

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What happens if both S and R inputs are 0 in an SR latch?

The output Q will remain unchanged

The output Q will be set to 1

The output Q will be reset to 0

The output Q will toggle between 0 and 1

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the main difference between SR flip flop and JK flip flop?

JK flip flop can handle the condition S=R=1, but SR flip flop cannot

JK flip flop has more number of inputs compared to SR flip flop

JK flip flop can toggle its output, but SR flip flop cannot

JK flip flop is faster than SR flip flop

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the solution to avoid race around condition in JK flip flop?

Decreasing the clock period t

Increasing the clock period t

Using edge trigger clock

Both a) and c)

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

How many stable states does a JK flip flop have?

1

2

3

4

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the main use of D flip flop?

To avoid the propagation delay

To overcome the racing condition

To store 1 bit of information

To store multiple bits of information

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