SYSTEM DESIGN THROUGH VERILOG

What are the possible values of == operator

• 0,1

• 0,x

• 1,x

• 0,1,x

What is the time period of clock #10 clock = ~clock

• 10

• 20

• .05

• .1

wait statement is

• edge sensitive bit

• level sensitive

• both

• none

Asynchronous reset is

• Clock dependent

• Clock independent

• Either

• None

For describing circuits like flip flops _____________ statement is used

• always

• assign

• initial

• forever

Which construct is used to execute loop fixed number of times

• while

• forever

• for

• none

RTL stands for _____________.

• resistor‐transfer logic

• register‐transistor logic

• register‐transfer logic

• none of these

What will the following code segment generate on synthesis?

always @(posedge clock)

begin

data3 <= din;

data2 <= data3;

data1 <= data2;

data0 <= data1;

end

• Four D flip-flops all fed with the data “din”.

• A 4-bit shift register.

• A 4-bit parallel-in parallel-out register.

• None of these.

Which of the following loops are

supported by verilog?

• if-else loop

• for loop

• while loop

• All the above

Which level of abstraction level is available in Verilog but not in VHDL?

• Behavioral level

• Structural level

• Dataflow level

• Switch level