Pseudo NMOS Logic Quiz

In a Pseudo-NMOS inverter, the pull-up transistor is:

• An enhancement-mode PMOS

• A depletion-mode NMOS

• A resistor

• A clocked NMOS

In a Pseudo-NMOS inverter, the PMOS transistor is:

• Connected to the clock

• Permanently ON

• Controlled by input logic

• Connected in series with NMOS

What happens to the output high voltage (VOHV_{OH}VOH​) in a pseudo-NMOS inverter when the NMOS is OFF?

• It is zero

• It is undefined

• It rises to VDDV_{DD}VDD​

• It is equal to the threshold voltage

Which factor significantly affects the output high voltage (VOHV_{OH}VOH​) in a pseudo-NMOS inverter?

• PMOS gate width

• NMOS gate capacitance

• Strength ratio of PMOS and NMOS

• Fan-out load only

The threshold voltage (VthV_{th}Vth​) of the inverter is typically:

• At VDD/2V_{DD}/2VDD​/2

• Higher than VDDV_{DD}VDD​

• Defined by NMOS alone

• Shifted due to always-on PMOS

Compared to CMOS inverter, the pseudo-NMOS inverter consumes:

• Less power

• No static power

• More static power

• Equal power

Which of the following best describes the operation of the pseudo-NMOS inverter at logic '0' input?

• Both NMOS and PMOS are OFF

• NMOS is ON, PMOS is OFF

• NMOS is OFF, PMOS is ON

• Both NMOS and PMOS are ON

The threshold point of a pseudo-NMOS inverter shifts towards:

• Ground

• VDDV_{DD}VDD​

• Midpoint of VDDV_{DD}VDD​

• Zero

Why does the pseudo-NMOS inverter not have rail-to-rail output swing?

• Due to clocked NMOS

• Because PMOS is weak

• Because NMOS is always OFF

• Because PMOS is always ON

What causes static power dissipation in pseudo-NMOS logic?

• Floating nodes

• Gate leakage

• Simultaneous conduction of PMOS and NMOS

• Slow rise time