Pseudo-NMOS Inverter Quiz

In a pseudo-NMOS inverter, the output low voltage (VOL) is primarily determined by:

• Strength of the PMOS transistor

• Load capacitance

• Resistance of the NMOS transistor

• Threshold voltage of the PMOS

When the input of a pseudo-NMOS inverter is high, the output:

• Floats

• Is pulled high

• Is pulled low by NMOS

• Is undefined

What causes the gain (dVout/dVin) of the pseudo-NMOS inverter to be highest?

• When Vin=0

• When Vin=VDD

• When Vin=Vth (threshold point)

• When both transistors are OFF

The gain at the gate threshold voltage in a pseudo-NMOS inverter is:

• Always zero

• Very low due to weak PMOS

• Very high due to strong transition region

• Independent of transistor sizing

A higher gain in the transition region of a pseudo-NMOS inverter leads to:

• Slower switching

• Sharper voltage transition (better noise margin)

• Lower power consumption

• Reduced output voltage swing

If the PMOS is weak (W/L = 2) and NMOS is strong (W/L = 10), what can be said about VOL?

• It will be close to VDD

• It will be midway between 0 and VDD

• It will be close to 0 V

• It will be equal to threshold voltage

Which of the following best explains a non-zero output low voltage (VOL) in pseudo-NMOS logic?

• Leakage current in PMOS

• Threshold mismatch

• Constant current through PMOS

• Body effect

What happens to VOL when PMOS width is increased significantly?

• It increases

• It decreases

• It remains constant

• It becomes undefined

What is the unit of gain at the gate threshold voltage in a pseudo-NMOS inverter?

• Volts

• Amperes

• Unitless

• V/V

The gain (dVout/dVin) is maximum at:

• Logic 1 input

• Logic 0 input

• Transition (threshold) region

• When PMOS is off