Microcontroller Unit 2:Architecture

Why might a CISC-based CPU be preferred in systems with limited memory register?

• It uses simplified instruction decoding

• It allows fewer instructions to perform complex tasks

• It has more general-purpose registers

• It uses a pipelining mechanism

A CPU needs to execute tasks with minimal clock cycles. Which architecture is more suitable and why?

• CISC, because of fewer instructions

• RISC, because instructions execute in a single clock cycle

• CISC, because of slower processing speed

• RISC, because the instruction set is longer

Compare RISC and CISC: Which trade-off is made in RISC to achieve faster execution speed?

• Uses fewer registers

• Increases cycles per instruction

• Requires more instructions to perform a task

• Executes multi-step operations in one instruction

In designing a real-time signal processing device, why would a Harvard architecture be more efficient than Von Neumann?

• It reduces hardware requirements

• It separates program and data memory, enabling simultaneous access

• It shares program and data memory which is faster

• It requires fewer control signals

When writing assembly code for a RISC-based system, what programming consideration must be taken into account?

• Each instruction performs multiple operations

• Additional instructions are needed to perform compound tasks

• Instruction size varies based on operation

• One instuction can perform one complete task

A developer wants to improve performance without increasing the number of instructions. Which architecture would be a better fit?

• RISC

• VLSI

• CISC

• LSI

How does the bus design in Harvard architecture enhance execution speed compared to Von Neumann architecture?

• By using one shared memory

• By simplifying hardware design

• By enabling parallel fetching of instructions and data

• By using fewer registers

In Von Neumann architecture, what is shared between data and instructions?

• CPU core

• Peripheral Address

• Memory Address

• Memory and bus

A programmer observes delays due to sequential instruction and data access. Which architectural change could reduce this bottleneck?

• Shift to Von Neumann architecture

• Add more general-purpose registers

• Adopt Harvard architecture for parallel access

• Use fewer data types in the program

A student wants to demonstrate how CISC and RISC handle the same arithmetic task. What key difference should they show in code?

• RISC will use a single instruction

• CISC will use more load/store instructions

• RISC will break the task into multiple simple instructions

• CISC will need multiple memory accesses