IHDL_MidterQuiz1

IHDL_MidterQuiz1

Professional Development

30 Qs

quiz-placeholder

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IHDL_MidterQuiz1

IHDL_MidterQuiz1

Assessment

Quiz

Computers

Professional Development

Practice Problem

Medium

Created by

Mel Bautista

Used 3+ times

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30 questions

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1.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

The basic unit or building block in Verilog is called a:

circuit

module

program

component

2.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

The correct syntax to declare an AND gate in Verilog is:

and (a, b, y);

and (y, a, b);

and y(a, b);

and (out=y, a, b);

3.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

Which data type is used to connect signals between gates in Verilog?

reg

int

wire

logic

4.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

Which of the following defines a 2-input OR gate named g1?

or g1 (y, a, b);

or (y, a, b);

or g1 y(a, b);

or #(y, a, b);

5.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

The statement not (y, a); represents:

y = a

y = NOT a

y = a OR b

y = a AND b

6.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

Which Verilog keyword starts the description of a module?

define

begin

module

start

7.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

Which keyword marks the end of a Verilog module?

end

endmodule

finish

done

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