IHDL_MidterQuiz1

The basic unit or building block in Verilog is called a:

• circuit

• module

• program

• component

The correct syntax to declare an AND gate in Verilog is:

• and (a, b, y);

• and (y, a, b);

• and y(a, b);

• and (out=y, a, b);

Which data type is used to connect signals between gates in Verilog?

• reg

• int

• wire

• logic

Which of the following defines a 2-input OR gate named g1?

• or g1 (y, a, b);

• or (y, a, b);

• or g1 y(a, b);

• or #(y, a, b);

The statement not (y, a); represents:

• y = a

• y = NOT a

• y = a OR b

• y = a AND b

Which Verilog keyword starts the description of a module?

• define

• begin

• module

• start

Which keyword marks the end of a Verilog module?

• end

• endmodule

• finish

• done

What will be the output of a 2-input NAND gate when both inputs are 1?

• 1

• 0

• Undefined

• X

The logic function of a NOR gate is:

• (A + B)’

• (A · B)’

• A + B

• A · B

Which gate outputs HIGH only when exactly one input is HIGH?

• XOR

• XNOR

• AND

• OR