Pipelining in Computer Architecture - MCQ Quiz

What are the five stages of a classic MIPS pipeline?

• Fetch, Decode, Execute, Memory, Store

• Instruction Fetch, Instruction Decode, Execute, Memory Access, Write Back

• Load, Decode, Compute, Write, Complete

• Read, Parse, Process, Access, Return

Which type of hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed?

• Structural hazard

• Control hazard

• Data hazard

• Pipeline hazard

What is the purpose of forwarding (data bypassing) in a pipelined processor?

• To eliminate all pipeline hazards

• To reduce the impact of data hazards by passing results directly between stages

• To predict branch outcomes

• To increase clock frequency

In a 5-stage pipeline with ideal conditions (no hazards), what is the theoretical CPI (Cycles Per Instruction)?

• 5

• 1

• 0.2

• Depends on instruction mix

Which hazard type is caused by branch instructions?

• Data hazard

• Structural hazard

• Control hazard

• Memory hazard

What is a "pipeline stall" or "bubble"?

• A complete shutdown of the pipeline

• A cycle where no useful work is done in one or more pipeline stages

• An optimization technique

• A type of cache miss

A load-use data hazard occurs when:

• Two instructions try to write to the same register

• An instruction immediately following a load tries to use the loaded data

• A branch instruction is executed

• The pipeline runs out of instructions

What technique helps mitigate control hazards in pipelined processors?

• Data forwarding

• Branch prediction

• Register renaming

• Cache optimization

• 200 million instructions/sec

• 500 million instructions/sec

• 1 billion instructions/sec

• 2.5 billion instructions/sec

Which of the following is NOT a common solution to structural hazards?

• Adding more hardware resources (duplicate units)

• Pipeline stalling

• Branch prediction

• Separate instruction and data caches