WorksheetsME6702 - Unit 3
Total questions: 17
Worksheet time: 9mins
In the I/O mode, the 8255 ports work as
reset pins
set pins
programmable I/O ports
only output ports
In BSR mode, which port can be used to
PORT A
PORT B
PORT C
The strobed input/output mode is another name of
Mode 0
Mode 1
Mode 2
None
The signals that are provided to maintain proper data flow and synchronization between the data transmitter and receiver are
handshaking signals
control signals
input signals
none
All I/O pins of 8255 has ______ d.c driving capacity
2.3 mA
2.5 mA
2.8 mA
2 mA
A low on this pin enables the communication between the 8255 and the CPU
A0
A1
CS
RD
If D3 = 0, D2 = 1 and D1 = 1, which pin of data bus line is selected
D0
D2
D3
D1
Settle down time for a mechanical key when pressed is,
10ms
15ms
25ms
20ms
For a common cathode configuration, to display an alphabet B using 7 segment LED, we have to give inputs to
a, f, g, c, d
a, f, g, c, d, e
f, g, c, d, e
a, b, c, d, e, f, g
In ADC, to select the input port 4, what is the value of the address line C, B, A
0 0 1
1 0 0
1 1 0
1 0 1
Which is not a technique in Digital to Analog Conversion
Weighted Resistor
R - 2R Ladder
Successive Approximation
Current O/P converter
The conversion delay in a successive approximation of an ADC 0808/0809 is
100 milliseconds
100 microseconds
50 milliseconds
50 milliseconds
The device that is used to obtain an accurate position control of rotating shafts in terms of steps is
DC motor
AC motor
Stepper motor
Servo motor
The data bus buffer is controlled by
control word register
read/write control logic
data bus
none of the mentioned
If A1=0, A0=1 then the input read cycle is performed from
port C to data bus
port B to data bus
port A to data bus
CWR to data bus
The function, ‘data bus tristated’ is performed when
CS(active low) = 1
CS(active low) = 0
CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
CS(active low) = 1 OR CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
The pin that clears the control word register of 8255 when enabled is
a)
b)
c)
d)
CLEAR
SET
CLK
RESET
