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WorksheetsCOA_Quiz (Phase-1)
Total questions: 137
Worksheet time: 2hrs 17mins
Name
Class
Date
1.
Your name: (First_name Last_name)
(eg. Pranav Tank)
4 lines
2.
Enrollment Number: (12 digits)
4 lines
3.
The fetch and execution cycles are interleaved with the help of ________
a)
Modification in processor architecture
b)
Clock
c)
Special unit
d)
Control unit
4.
The computer architecture aimed at reducing the time of execution of instructions is ________
a)
CISC
b)
RISC
c)
ISA
d)
ANNA
5.
Devices that are used primarily to transport data between the processor and the user are known as:
a)
Networking devices
b)
Basic storage devices
c)
Data transfer device
d)
Data Presentation Device
6.
_______ is concerned with the way the hardware components operate to form computer system.
a)
Computer design
b)
Computer architecture
c)
Computer implementation
d)
Computer Organization
7.
Pipe lining increases the CPU instruction:
a)
efficiency
b)
latency
c)
both a and b
d)
Throughput
8.
The NOR gate is complement of:
a)
AND gate
b)
OR Gate
c)
NAND gate
d)
NOT gate
9.
A _____ is a digital circuit that performs the inverse operation of decodes
a)
multiplexer
b)
adder
c)
subtractor
d)
encoder
10.
SIMD stands for:
a)
Multiple Instruction Streams and Single Data Stream
b)
Single Instruction Stream Over Media Data Streams
c)
Single Instruction Stream Over Minimum Data Streams
d)
Single Instruction Stream Over Multiple Data Streams
11.
The computer code for the interchange of information between terminal is:
a)
BCD
b)
EBCDIC
c)
ASCII
d)
All of the above
12.
The I/O processor has a direct access to _____ and contains a number of independent data channels:
a)
main memory
b)
secondary memory
c)
flash memory
d)
cache
13.
The address mapping is done, when the program is initially loaded is called:
a)
dynamic relocation
b)
static relocation
c)
dynamic as well as static relocation
d)
relocation
14.
The channel which handles the multiple requests and multiplexes the data transfers from these devices a byte at a time is known as:
a)
the selector channel
b)
block multiplex channel
c)
multiplexer channel
d)
None of the above
15.
A computer program that converts an entire program into machine language at one time is called:
a)
interpreter
b)
simulator
c)
commander
d)
compiler
16.
A micro program is sequencer perform the operation:
a)
Read
b)
Write
c)
Read and Write
d)
Read and Execute
17.
When the CPU detects an interrupt, it then saves its:
a)
Previous State
b)
Next State
c)
Current State
d)
All of the above
18.
An exception conditions in a computer system by an event external to the CPU is called:
a)
Halt
b)
Interrupt
c)
Wait
d)
Process
19.
Striking key stores the corresponding character code in a 8-bit buffer register associated with the keyboard. This register is called as:
a)
Data in out
b)
Data out
c)
Data In
d)
None of the above
20.
Memory access in RISC architecture is limited to instructions:
a)
CALL and RET
b)
MOV and JMP
c)
Push and Pop
d)
STA and LDA
21.
A simple way of performing I/O tasks is to use a method known as:
a)
program-controlled input
b)
program-controlled output
c)
I/O operation
d)
program-controlled input/output
22.
Interrupts which are initiated by an instruction are:
a)
internal
b)
external
c)
hardware
d)
software
23.
The addressing mode used in an instruction of the form ADD X Y, is
a)
Absolute
b)
indirect
c)
index
d)
None of these
24.
Von Neumann architecture is
a)
SISD
b)
SIMD
c)
MISD
d)
MIMD
25.
Cache memory acts between
a)
CPU and RAM
b)
RAM and ROM
c)
CPU and Hard Disk
d)
None of these
26.
Virtual memory consists of
a)
Magnetic memory
b)
Dynamic RAM
c)
Static RAM
d)
None of these
27.
In a program using subroutine call instruction, it is necessary
a)
initialise program counter
b)
Clear the accumulator
c)
Reset the microprocessor
d)
Clear the instruction register
28.
A Stack-organised Computer uses instruction of
a)
Zero addressing
b)
Indirect addressing
c)
Two-addressing
d)
Index addressing
29.
When CPU is executing a Program that is part of the Operating System, it is said to be in _______
a)
Interrupt mode
b)
System mode
c)
Half mode
d)
Simplex mode
30.
Cache memory works on the principle of
a)
Locality of data
b)
Locality of memory
c)
Locality of reference
d)
Locality of reference & memory
31.
The main memory in a Personal Computer (PC) is made of
a)
cache memory
b)
static RAM
c)
Dynamic Ram
d)
Both Cache & Static Ram
32.
PSW is saved in stack when there is a
a)
interrupt recognised
b)
execution of RST instruction
c)
Execution of CALL instruction
d)
All of these
33.
The circuit converting binary data in to decimal is
a)
Encoder
b)
Multiplexer
c)
Decoder
d)
Code converter
34.
Memory unit accessed by content is called
a)
Read only memory
b)
Programmable Memory
c)
Virtual Memory
d)
Associative Memory
35.
The BSA instruction is
a)
Branch and store accumulator
b)
Branch and save return address
c)
Branch and shift address
d)
Branch and show accumulator
36.
Arithmetic operations with fixed point numbers take longer time for execution as compared to with floating point numbers.
a)
true
b)
false
c)
Maybe
d)
Not always
37.
Status bit is also called
a)
Binary bit
b)
Signed bit
c)
Flag bit
d)
Unsigned bit
38.
If the value V(x) of the target operand is contained in the address field itself, the addressing mode is
a)
immediate
b)
direct
c)
indirect
d)
implied
39.
PC Program Counter is also called
a)
instruction pointer
b)
memory pointer
c)
file pointer
d)
data counter
40.
CPU does not perform the operation:
a)
data transfer
b)
logic operation
c)
arithmetic operation
d)
all of the above
41.
The communication between central system and the outside environment is done by:
a)
Control system
b)
Logic system
c)
Memory system
d)
I/O subsystem
42.
Which registers can interact with the secondary storage ?
a)
IR
b)
PC
c)
MAR
d)
None of these
43.
The return address of the Sub-routine is pointed to by ?
a)
IR
b)
PC
c)
MAR
d)
None of these
44.
In case of nested subroutines the return addresses are stored in __________
a)
System heap
b)
Special memory buffers
c)
Registers
d)
Processor stack
45.
RTN stands for _____
a)
Register Transfer Notation
b)
Register Transmission Notation
c)
Regular Transmission Notation
d)
Regular Transfer Notation
46.
A source program is usually in _______
a)
Assembly language
b)
Machine level language
c)
High-level language
d)
Natural language
47.
The instruction, Add R1,R2,R3 in RTN is _______
a)
R3=R1+R2+R3
b)
R3<-[R1]+[R2]+[R3]
c)
R3=[R1]+[R2]
d)
R3<-[R1]+[R2]
48.
Which of the following techniques used to effectively utilize main memory?
a)
Address binding
b)
Dynamic linking
c)
Dynamic loading
d)
Both Dynamic linking and loading
49.
The instructions which can be run only supervisor mode are?
a)
Non-privileged instructions
b)
System instructions
c)
Privileged instructions
d)
Exception instructions
50.
The two phases of executing an instruction are ______
a)
Instruction decoding and storage
b)
Instruction fetch and instruction execution
c)
Instruction execution and storage
d)
Instruction fetch and Instruction processing
51.
In a system, which has 32 registers the register id is __________ long.
a)
16 bits
b)
8 bits
c)
5 bits
d)
6 bits
52.
The ALU makes use of _______ to store the intermediate results.
a)
Accumulators
b)
Registers
c)
Stack
d)
Heap
53.
The condition flag Z is set to 1 to indicate __
a)
The operation has resulted in an error
b)
The operation requires an interrupt call
c)
The result is zero
d)
There is no empty register available
54.
What are the different modes of operation of a computer?
a)
User and System mode
b)
Supervisor and Trace mode
c)
User and Supervisor mode
d)
Supervisor, User and Trace mode
55.
The control unit controls other units by generating ______
a)
Control signals
b)
Timing signals
c)
Command Signals
d)
Transfer signals
56.
The time delay between two successive initiations of memory operation _____
a)
Memory access time
b)
Instruction delay
c)
Memory search time
d)
Memory cycle time
57.
In DMA transfers, the required signals and addresses are given by the ____
a)
Processor
b)
Device drivers
c)
DMA controllers
d)
Program itself
58.
The fetch and execution cycles are interleaved with the help of ________
a)
Modification in processor architecture
b)
Clock
c)
Special unit
d)
Control unit
59.
The computer architecture aimed at reducing the time of execution of instructions is ________
a)
CISC
b)
RISC
c)
ISA
d)
ANNA
60.
Devices that are used primarily to transport data between the processor and the user are known as:
a)
Networking devices
b)
Basic storage devices
c)
Data transfer device
d)
Data Presentation Device
61.
_______ is concerned with the way the hardware components operate to form computer system.
a)
Computer design
b)
Computer architecture
c)
Computer implementation
d)
Computer Organization
62.
Pipe lining increases the CPU instruction:
a)
efficiency
b)
latency
c)
both a and b
d)
Throughput
63.
The NOR gate is complement of:
a)
AND gate
b)
OR Gate
c)
NAND gate
d)
NOT gate
64.
A _____ is a digital circuit that performs the inverse operation of decodes
a)
multiplexer
b)
adder
c)
subtractor
d)
encoder
65.
SIMD stands for:
a)
Multiple Instruction Streams and Single Data Stream
b)
Single Instruction Stream Over Media Data Streams
c)
Single Instruction Stream Over Minimum Data Streams
d)
Single Instruction Stream Over Multiple Data Streams
66.
The computer code for the interchange of information between terminal is:
a)
BCD
b)
EBCDIC
c)
ASCII
d)
All of the above
67.
The I/O processor has a direct access to _____ and contains a number of independent data channels:
a)
main memory
b)
secondary memory
c)
flash memory
d)
cache
68.
The address mapping is done, when the program is initially loaded is called:
a)
dynamic relocation
b)
static relocation
c)
dynamic as well as static relocation
d)
relocation
69.
The channel which handles the multiple requests and multiplexes the data transfers from these devices a byte at a time is known as:
a)
the selector channel
b)
block multiplex channel
c)
multiplexer channel
d)
None of the above
70.
A computer program that converts an entire program into machine language at one time is called:
a)
interpreter
b)
simulator
c)
commander
d)
compiler
71.
A micro program is sequencer perform the operation:
a)
Read
b)
Write
c)
Read and Write
d)
Read and Execute
72.
When the CPU detects an interrupt, it then saves its:
a)
Previous State
b)
Next State
c)
Current State
d)
All of the above
73.
An exception conditions in a computer system by an event external to the CPU is called:
a)
Halt
b)
Interrupt
c)
Wait
d)
Process
74.
Striking key stores the corresponding character code in a 8-bit buffer register associated with the keyboard. This register is called as:
a)
Data in out
b)
Data out
c)
Data In
d)
None of the above
75.
Memory access in RISC architecture is limited to instructions:
a)
CALL and RET
b)
MOV and JMP
c)
Push and Pop
d)
STA and LDA
76.
A simple way of performing I/O tasks is to use a method known as:
a)
program-controlled input
b)
program-controlled output
c)
I/O operation
d)
program-controlled input/output
77.
Interrupts which are initiated by an instruction are:
a)
internal
b)
external
c)
hardware
d)
software
78.
The addressing mode used in an instruction of the form ADD X Y, is
a)
Absolute
b)
indirect
c)
index
d)
None of these
79.
Von Neumann architecture is
a)
SISD
b)
SIMD
c)
MISD
d)
MIMD
80.
Cache memory acts between
a)
CPU and RAM
b)
RAM and ROM
c)
CPU and Hard Disk
d)
None of these
81.
Virtual memory consists of
a)
Magnetic memory
b)
Dynamic RAM
c)
Static RAM
d)
None of these
82.
In a program using subroutine call instruction, it is necessary
a)
initialise program counter
b)
Clear the accumulator
c)
Reset the microprocessor
d)
Clear the instruction register
83.
A Stack-organised Computer uses instruction of
a)
Zero addressing
b)
Indirect addressing
c)
Two-addressing
d)
Index addressing
84.
When CPU is executing a Program that is part of the Operating System, it is said to be in _______
a)
Interrupt mode
b)
System mode
c)
Half mode
d)
Simplex mode
85.
Cache memory works on the principle of
a)
Locality of data
b)
Locality of memory
c)
Locality of reference
d)
Locality of reference & memory
86.
The main memory in a Personal Computer (PC) is made of
a)
cache memory
b)
static RAM
c)
Dynamic Ram
d)
Both Cache & Static Ram
87.
PSW is saved in stack when there is a
a)
interrupt recognised
b)
execution of RST instruction
c)
Execution of CALL instruction
d)
All of these
88.
The circuit converting binary data in to decimal is
a)
Encoder
b)
Multiplexer
c)
Decoder
d)
Code converter
89.
Memory unit accessed by content is called
a)
Read only memory
b)
Programmable Memory
c)
Virtual Memory
d)
Associative Memory
90.
The BSA instruction is
a)
Branch and store accumulator
b)
Branch and save return address
c)
Branch and shift address
d)
Branch and show accumulator
91.
Arithmetic operations with fixed point numbers take longer time for execution as compared to with floating point numbers.
a)
true
b)
false
c)
Maybe
d)
Not always
92.
Status bit is also called
a)
Binary bit
b)
Signed bit
c)
Flag bit
d)
Unsigned bit
93.
If the value V(x) of the target operand is contained in the address field itself, the addressing mode is
a)
immediate
b)
direct
c)
indirect
d)
implied
94.
PC Program Counter is also called
a)
instruction pointer
b)
memory pointer
c)
file pointer
d)
data counter
95.
CPU does not perform the operation:
a)
data transfer
b)
logic operation
c)
arithmetic operation
d)
all of the above
96.
The communication between central system and the outside environment is done by:
a)
Control system
b)
Logic system
c)
Memory system
d)
I/O subsystem
97.
Which registers can interact with the secondary storage ?
a)
IR
b)
PC
c)
MAR
d)
None of these
98.
The return address of the Sub-routine is pointed to by ?
a)
IR
b)
PC
c)
MAR
d)
None of these
99.
In case of nested subroutines the return addresses are stored in __________
a)
System heap
b)
Special memory buffers
c)
Registers
d)
Processor stack
100.
RTN stands for _____
a)
Register Transfer Notation
b)
Register Transmission Notation
c)
Regular Transmission Notation
d)
Regular Transfer Notation
101.
A source program is usually in _______
a)
Assembly language
b)
Machine level language
c)
High-level language
d)
Natural language
102.
The instruction, Add R1,R2,R3 in RTN is _______
a)
R3=R1+R2+R3
b)
R3<-[R1]+[R2]+[R3]
c)
R3=[R1]+[R2]
d)
R3<-[R1]+[R2]
103.
Which of the following techniques used to effectively utilize main memory?
a)
Address binding
b)
Dynamic linking
c)
Dynamic loading
d)
Both Dynamic linking and loading
104.
The instructions which can be run only supervisor mode are?
a)
Non-privileged instructions
b)
System instructions
c)
Privileged instructions
d)
Exception instructions
105.
The two phases of executing an instruction are ______
a)
Instruction decoding and storage
b)
Instruction fetch and instruction execution
c)
Instruction execution and storage
d)
Instruction fetch and Instruction processing
106.
In a system, which has 32 registers the register id is __________ long.
a)
16 bits
b)
8 bits
c)
5 bits
d)
6 bits
107.
The ALU makes use of _______ to store the intermediate results.
a)
Accumulators
b)
Registers
c)
Stack
d)
Heap
108.
The condition flag Z is set to 1 to indicate __
a)
The operation has resulted in an error
b)
The operation requires an interrupt call
c)
The result is zero
d)
There is no empty register available
109.
What are the different modes of operation of a computer?
a)
User and System mode
b)
Supervisor and Trace mode
c)
User and Supervisor mode
d)
Supervisor, User and Trace mode
110.
The control unit controls other units by generating ______
a)
Control signals
b)
Timing signals
c)
Command Signals
d)
Transfer signals
111.
The time delay between two successive initiations of memory operation _____
a)
Memory access time
b)
Instruction delay
c)
Memory search time
d)
Memory cycle time
112.
In DMA transfers, the required signals and addresses are given by the ____
a)
Processor
b)
Device drivers
c)
DMA controllers
d)
Program itself
113.
The address mapping is done, when the program is initially loaded is called:
a)
dynamic relocation
b)
relocation
c)
dynamic as well as static relocation
d)
static relocation
114.
The main advantage of multiple bus organization over a single bus is ____
a)
Reduction in the number of cycles for execution
b)
Increase in size of the registers
c)
Better Connectivity
d)
None of the mentioned
115.
In computers, subtraction is generally carried out by
a)
9’s complement
b)
2’s complement
c)
10’s complement
d)
1’s complement
116.
Which of the following is lowest in memory hierarchy?
a)
Cache memory
b)
Registers
c)
Secondary memory
d)
RAM
117.
The instruction ‘ORG O’ is a
a)
Machine Instruction
b)
Pseudo instruction
c)
High level instruction
d)
Memory instruction
118.
A floating point number that has a O in the MSB of mantissa is said to have
a)
Overflow
b)
Underflow
c)
Undefined
d)
Important number
119.
The time interval between adjacent bits is called the
a)
Word-time
b)
Slice time
c)
Bit-time
d)
Turn-around time
120.
A group of bits that tell the computer to perform a specific operation is known as
a)
Instruction code
b)
Accumulator
c)
Micro-operation
d)
Register
121.
The load instruction is mostly used to designate a transfer from memory to a processor register known as
a)
Accumulator
b)
Instruction Register
c)
Memory address Register
d)
Program counter
122.
The communication between the components in a microcomputer takes place via the address and
a)
I/O bus
b)
Data bus
c)
Control lines
d)
Address bus
123.
An instruction pipeline can be implemented by means of
a)
LIFO buffer
b)
FIFO buffer
c)
Stack
d)
None of the above
124.
A flip-flop is a binary cell capable of storing information of
a)
One bit
b)
Zero bit
c)
Byte
d)
Eight bit
125.
Microinstructions are stored in control memory groups, with each group specifying a ____
a)
Routine
b)
Subroutine
c)
Vector
d)
Address
126.
The instruction in different stages of the pipeline do not interfere with one another, the separation is done by ______
a)
Pipe stages
b)
Pipeline stacks
c)
Pipeline registers
d)
Processor cycles
127.
The system bus is made up of
a)
Data bus
b)
Data bus and Address bus
c)
Data bus and Control bus
d)
Data bus, Address bus and Control bus
128.
Booth’s Algorithm is used in floating-point
a)
Addition
b)
Subtraction
c)
Multiplication
d)
Division
129.
The process that periodically checks the status of an I/O devices, is known as
a)
Cold Swapping
b)
I/O instructions
c)
Polling
d)
Dealing
130.
For the operation of multiplication hardware needs minimum ALU of
a)
16bits
b)
32bits
c)
64bits
d)
128bits
131.
The most relevant addressing mode to write position-independent codes is
a)
Direct mode
b)
Indirect mode
c)
Relative mode
d)
Indexed mode
132.
Which memory is difficult to interface with the processor?
a)
RAM
b)
ROM
c)
Static Memory
d)
Dynamic Memory
133.
Which of the following is not included in the memory write operation
a)
MAR
b)
PC
c)
MDR
d)
Data bus
134.
Hexadecimal number that this binary number (0001 0011 0111)2 represent is
a)
123
b)
135
c)
145
d)
137
135.
The register used to store the flags is called as _____
a)
Flag register
b)
Status register
c)
Test register
d)
Log register
136.
________ bus structure is usually used to connect I/O devices.
a)
Single bus
b)
Multiple bus
c)
Star bus
d)
Rambus
137.
The Input devices can send information to the processor
a)
When the SIN status flag is set
b)
When the data arrives regardless of the SIN flag
c)
Neither of the cases
d)
Either of the cases
Reset
