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Worksheets

VLSI

Total questions: 80

Worksheet time: 1hrs 20mins

Name
Class
Date
1.
Doubling the amount of transistors in every 18 months, is known as
a)
Gordan’s Law
b)
More’s Law
c)
Moor’s Law
d)
None of these
2.
_______________in design means that the various functional blocks which make up the larger system must have well-defined functions and interfaces.
a)
Regularity
b)
Hierarchy
c)
Locality
d)
Modularity
3.
The chip yield can be further divided into ________ subcategories:
a)
3
b)
4
c)
2
d)
None of these
4.
The _______________ test weeds out the problems of shorts, opens and leakage current, and can detect logic and circuit design faults.
a)
Parametric
b)
Functional
c)
Circuit
d)
None of these
5.
The Y-chart consists of _____________ major domains.
a)
6
b)
5
c)
4
d)
3
6.

The IC package pins can be directly soldered on the PCB; this method is called

a)

surface-mounted technology

b)

surface-mounted technique

c)

surface-module technology

d)

surface-mounted technique

7.
The maximum pin count of DIP is typically limited to ___________.
a)
32
b)
64
c)
128
d)
94
8.
In which design all circuitry and all interconnections are designed?
a)
full custom design
b)
semi-custom design
c)
gate array design
d)
transistor design
9.

In which method regularity is used to reduce complexity?

a)

random approach

b)

hierarchical approach

c)

algorithmic approach

d)

semi-design approach

10.
The n-type region created near the surface by the positive gate bias is called the inversion layer, and this condition is called ___________________.
a)
Channel inversion
b)
accumulation
c)
Surface inversion
d)
depletion
11.
the surface is said to be ____________ when the density of mobile electrons on the surface becomes equal to the density of holes in the bulk (p-type) substrate.
a)
(i) accumulated
b)
(ii) inverted
c)
both (i) and (ii)
d)
None of these
12.
the surface is said to be inverted when
a)
the density of mobile electrons on the surface becomes equal to the density of holes in the bulk (p-type) substrate.
b)
the density of mobile electrons on the surface becomes greater than to the density of holes in the bulk (p-type) substrate.
c)
the density of mobile electrons on the surface becomes less than to the density of holes in the bulk (p-type) substrate.
d)
None of these
13.
The simple operation principle of nMOS device is: control the current conduction between the source and the drain, using the electric field generated by the gate _________ as a control variable.
a)
current
b)
power
c)
voltage
d)
None of these
14.
the channel current also called the _______ current
a)
drain
b)
gate
c)
substrate
d)
source
15.
The substrate bias coefficient is __________ in nMOS, ___________ in pMOS.
a)
negative, positive
b)
positive, negative
c)
positive, positive
d)
negative, negative
16.

the threshold voltage of an enhancement-type n-channel MOSFET is a _________ quantity, whereas the threshold voltage of a p-channel MOSFET is___________.

a)

positive, negative

b)

negative, positive

c)

negative, negative

d)

positive, positive

17.
The substrate Fermi potential OF is _________ in nMOS, __________ in pMOS.
a)
positive, negative
b)
positive, positive
c)
negative, negative
d)
negative, positive
18.

for VDS = VDSAT, the inversion charge at the drain is reduced to zero, which is called the _____________ point

a)

Saturation

b)

Linear

c)

Cut-off

d)

pinch-off

19.
as the drain voltage is increased, the inversion layer charge and the channel depth at the drain end _______________.
a)
start to decrease
b)
start to increase
c)
remain the same
d)
None of these
20.
nMOS devices are formed in
a)
p-type substrate of high doping level
b)
n-type substrate of low doping level
c)
p-type substrate of moderate doping level
d)
n-type substrate of high doping level
21.

Source and drain in nMOS device are isolated by

a)

a single diode

b)

two diodes

c)

three diodes

d)

four diodes

22.

In depletion mode, source and drain are connected by

a)

insulating channel

b)

conducing channel

c)

Vdd

d)

Vss

23.
The condition for non saturated region is
a)
Vds = Vgs – Vt
b)
Vgs lesser than Vt
c)
Vds lesser than Vgs – Vt
d)
Vds greater than Vgs – Vt
24.
In enhancement mode, device is in _________ condition
a)
conducting
b)
non conducting
c)
partially conducting
d)
insulating
25.

MOS transistor structure is

a)

symmetrical

b)

non symmetrical

c)

semi symmetrical

d)

pseudo symmetrical

26.

Inversion layer in enhancement mode consists of excess of

a)

positive carriers

b)

negative carriers

c)

both in equal quantity

d)

neutral carriers

27.

Source in nMOS transistors is doped with ______ material

a)

n-type

b)

p-type

c)

n & p type

d)

none of the mentioned

28.
If the gate is given sufficiently large charge, electrons will be attracted to
a)
drain region
b)
channel region
c)
switch region
d)
bulk region
29.
Enhancement mode device acts as ____ switch, depletion mode acts as _____ switch
a)
open, closed
b)
closed, open
c)
open, open
d)
close, close
30.

Depletion mode MOSFETs are more commonly used as

a)

switches

b)

resistors

c)

buffers

d)

capacitors

31.
In linear region, ______ channel exists
a)
uniform
b)
non-uniform
c)
wide
d)
uniform and wide
32.
MOSFET is used as
a)
current source
b)
voltage source
c)
buffer
d)
divider
33.
According to body effect, substrate is biased with respect to
a)
source
b)
drain
c)
gate
d)
Vss
34.
Increasing Vsb, _______ the threshold voltage
a)
does not effect
b)
decreases
c)
increases
d)
exponentially increases
35.

Ids is _______ to length L of the channel

a)

directly proportional

b)

inversely proportional

c)

not related

d)

logarithmically related

36.
The MOS transistor is non conducting when
a)
zero source bias
b)
zero threshold voltage
c)
zero gate bias
d)
zero drain bias
37.
Inverters are essential for
a)
NAND gates
b)
NOR gates
c)
sequential circuits
d)
all of the mentioned
38.
In basic inverter circuit, ______ is connected to ground
a)
source
b)
gates
c)
drain
d)
resistance
39.
In inverter circuit, ________ transistors is used as load
a)
enhancement mode
b)
depletion mode
c)
all of the mentioned
d)
none of the mentioned
40.
For depletion mode transistor, gate should be connected to
a)
source
b)
drain
c)
substrate
d)
positive voltage rail
41.
Pass transistors are transistors used as
a)
switches connected in series
b)
switches connected in parallel
c)
inverters used in series
d)
inverter used in parallel
42.
resistive load inverter has ______ regions of operation
a)
three
b)
four
c)
two
d)
five
43.
CMOS inverter has ______ regions of operation
a)
three
b)
four
c)
two
d)
five
44.
If n-transistor conducts and has large voltage between source and drain, then it is said to be in _____ region
a)
linear
b)
saturation
c)
non saturation
d)
cut-off
45.
Gate area can be given as
a)
L/W
b)
L * W
c)
2L/W
d)
L/2W
46.
In Full scaling saturation current is scaled by
a)
S
b)
1/(S*S)
c)
1/S
d)
S*S
47.
In constant-voltage scaling Linear current is scaled by
a)
S
b)
1/(S*S)
c)
1/S
d)
S*S
48.
In constant-voltage scaling Vgs is scaled by
a)
S
b)
1/(S*S)
c)
1/S
d)
None of these
49.
In Full scaling Doping densities is scaled by
a)
S
b)
1/(S*S)
c)
1/S
d)
S*S
50.
In Full scaling Power dissipation is scaled by
a)
S
b)
1/(S*S)
c)
1/S
d)
S*S
51.
The size of a transistor is usually defined in terms of its
a)
channel length
b)
feature size
c)
width
d)
thickness ‘d’
52.
Cross section area is scaled by
a)
S
b)
1/(S*S)
c)
1/S
d)
S*S
53.

In CMOS logic circuit the n-MOS transistor acts as:

a)

Load

b)

Pull up network

c)

Pull down network

d)

Not used in CMOS circuits

54.
In CMOS logic circuit the p-MOS transistor acts as:
a)
Pull down network
b)
Pull up network
c)
driver
d)
Short to ground
55.

The capacitances in MOSFET occurs due to:

a)

Interconnects

b)

Difference in Doping concentration

c)

Difference in dopant materials

d)

All of the mentioned

56.
The parasitic capacitances found in MOSFET are:
a)
Oxide related capacitances
b)
Inter electrode capacitance
c)
Electrolytic capacitance
d)
All of the mentioned
57.
In Cut-off Mode, the capacitance Cgs will be equal to:
a)
2Cgd
b)
0
c)
Cgb
d)
All of the mentioned
58.
In cut-off mode, the value of gate to substrate capacitance is equal to:
a)
Cox .(W- L)
b)
Cox W/ L
c)
Cox* W*L
d)
0
59.
When MOSFET is operating in saturation region, the gate to source capacitance is :
a)
1/2*Cox*W*L
b)
2/3*Cox*W*L
c)
Cox*W*L
d)
1/3*Cox*W*L
60.
Observability is the process of
a)
checking all inputs
b)
checking all outputs
c)
checking all possible inputs
d)
checking errors and performance
61.

The design technique helps in improving

a)

controllability

b)

observability

c)

controllability and observability

d)

overall performance

62.

Storage elements in scan design technique is reconfigured to form

a)

RAM

b)

shift registers

c)

buffers

d)

amplifiers

63.
Built-in self test aims to
a)
reduce test pattern generation cost
b)
reduce volume of test data
c)
reduce test time
d)
all of the mentioned
64.
In external feedback LFSR, shift registers and feedback paths are combined using
a)
OR gates
b)
AND gates
c)
EX-OR gates
d)
NAND gates
65.
______ determines the position of EX-OR gate with respect to fip-flops
a)
maximal length sequence<br />
b)
value of n
c)
number of flip-flops
d)
characteristic equation
66.

Signature analysis performs

a)

addition

b)

multiplication

c)

polynomial division

d)

amplifies

67.
The ease with which the controller establish specific signal value at each node by setting input values is known as:<br />
a)
Testability
b)
Observability
c)
Controllability
d)
Manufacturability
68.

The ease with which the controller determines signal value at any node by setting input values is known as:

a)

Testability

b)

Observability

c)

Controllability

d)

Manufacturability

69.

Divide and Conquer approach to large and complex circuits for testing is found in:

a)

Partition and Mux Technique

b)

Simplified automatic test pattern generation technique

c)

Scan based technique

d)

All of the mentioned

70.
Surface inversion occurs when gate voltage is:
a)
Less than zero
b)
Less than threshold voltage
c)
Equal to threshold voltage
d)
Greater than threshold voltage
71.

The threshold voltage depends on:

a)

The workfunction difference between gate and channel

b)

The gate voltage component to change surface potential

c)

The gate voltage component to offset the depletion charge and fixed charges in gate oxide

d)

All of the mentioned

72.

The expression for threshold voltage for the enhancement mode nMOSFET is :

a)

Φgc-2ϕf-Qbo/Cox-Qox/Cox

b)

Φgc+ϕf-Qbo/Cox

c)

Φgc-ϕf-Qbo/Cox+Qox/Cox

d)

Φgc+2ϕf-Qbo/Cox-Qox/Cox

73.

The CMOS inverter consist of:

a)

Enhancement mode n-MOS transistor and depletion mode p-MOS transistor

b)

Enhancement mode p-MOS transistor and depletion mode n-MOS transistor

c)

Enhancement mode p-MOS transistor and enhancement mode p-MOS transistor

d)

Enhancement mode p-MOS transistor and enhancement mode n-MOS transistor

74.
In the CMOS inverter the output voltage is measured across:
a)
Drain of n-MOS transistor and ground
b)
Source of p-MOS transistor and ground
c)
Source of n-MOS transistor and source of p-MOS transistor
d)
Gate of p-MOS transistor and Gate of n-MOS transistor
75.

When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, the transistors are operating in:

a)

N-MOS is cutoff, p-MOS is in Saturation

b)

P-MOS is cutoff, n-MOS is in Saturation

c)

Both the transistors are in linear region

d)

Both the transistors are in saturation region

76.

In MOSFET devices the N-channel type is better than the P – Channel type in the following respects.

a)

It has better immunity

b)

It is faster

c)

It is TTL compatible

d)

It has better drive capability

77.

Which transistor element is used in CMOS logic?

a)

FET

b)

MOSFET

c)

Bipolar

d)

Unijunction

78.

Which equation is correct?

a)

NML = VIL(max) + VOL(max)

b)

NMH= VOH(min) + VIH(min)

c)

NML = VOH(min) – VIH(min)

d)

NMH = VOH(min) – VIH(min)

79.

In basic inverter circuit, ______ is connected to ground

a)

source

b)

gates

c)

drain

d)

resistance

80.

The basic figures of merit for MOS devices are :

a)

Minimum Feature size

b)

Low Power dissipation

c)

Maximum operational frequency

d)

All of the mentioned

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