always construct is Synthesizable

#5 is Synthesizable

= and <= represent

Verilog is an

Integer datatype is allocated ______ number of bits

reg [4:1] pwm will initialize variable of _______ bits

{,} is used to perform which operation

The most appropriate modeling style to implement Traffic light controller will be

{1'b0, 2'b01, 3'b0} will result in

Shivani wish to implement 4:1 mux. Identify the errors in the line numbers of the code

Nitin Wish to implement Arithmetic unit capable of performing add, sub, mul and div operation. He written the following code identify the line numbers on which error exists.

Vishwesh wish to implement D-flipflop with clear input. So if clear is high he want the output to be zero else D-fliflop must follow Din. He written the following code identify the line numbers on which error exists.

Sumedh wish to implement 4-bit Synchronous Up/Down Counter. If reset state is high counter will reset to zero else depending on the mode pin state it will count up or Down. He decided that if Mode state is high then Counter will count up else vice versa.

Gaurav wish to implement Half adder. He written the following code identify the line numbers on which error exists.